Revision 3.03 – May 25, 2007
S1220 – SONET/SDH/ATM Quad OC-3/12
with Clock Data Recovery (CDR)
Advance Data Sheet
Figure 13. RESET Requirement
REFCLKP INPUT
t
RSTB
t > 0
Note: RSTB active should extend over at least two REFCLK rising edges t>0.
Power up requires core reset
A loss of REFCLK requires core reset.
Table 30. RESET Specification
Parameter
Description
Minimum Rest Value
Min
Max
Units
Conditions
Reset
29
ns
Measured from the midpoint of the signal.
(77.76 MHz REFCLK)
= (1/77.76 MHz)*2 + 3 ns= 29 ns
Table 31. MDIO Timing Characteristics
Unit
Parameter
Description
Min
Typ
Max
Conditions
s
t
Input set-up time from MDIO to MDC
Input hold time from MDIO to MDC
MDC to MDIO Clock to data delay
10
10
15
ns
ns
SU
t
H
t
80
10
6
ns
Delay
MDC frequency
MHz
Input Capacitance
Bus Loading Capacitance
pF
pF
Guaranteed by design but not tested.
Guaranteed by design but not tested.
60
36
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