Revision 3.03 – May 25, 2007
S1220 – SONET/SDH/ATM Quad OC-3/12
with Clock Data Recovery (CDR)
Advance Data Sheet
Figure 6. Jitter Transfer Specification
CHARACTERISTICS
Performance
The S1220 PLL complies with the jitter specifications
proposed for SONET/SDH equipment as defined by
Table 2.
P
slope = -20 dB/decade
Jitter Transfer
Jitter
Acceptable
Transfer
Jitter transfer function is defined as the ratio of jitter on
the output OC-N/STS-N signal to the jitter applied on
the input OC-N/STS-N signal versus jitter frequency.
Jitter transfer requirements are shown in Figure 6. The
measurement condition is that input sinusoidal jitter up
to the mask level in Figure 5 be applied for each of the
OC-N/STS-N rates. S1220 input jitter tolerance speci-
fications are shown in Table 8.
Range
fc
Frequency
OC/STS
fc
P
Level
(kHz)
(dB)
Input Jitter Tolerance
12
500
130
0.1
0.1
Input jitter tolerance is defined as the peak to peak
amplitude of sinusoidal jitter applied on the input signal
that causes an equivalent 1 dB optical/electrical power
penalty. SONET input jitter tolerance requirements are
shown in Figure 5.
3
Table 8. Jitter Tolerance S1220 Specification
Parameter Min Typ Units Conditions
Jitter Generation
Jitter
Tolerance
STS-12
0.4
1.5
15
0.65
4
UI
UI
UI
UI
UI
UI
250 kHz < f < 5 MHz
300 Hz < f < 25 kHz
10 Hz < f < 30 Hz
The jitter generation of the serial clock and serial data
outputs shall not exceed the value specified in
Table 14.
20
0.8
5
Figure 5. Input Jitter Tolerance
Jitter
Tolerance
STS-3
0.4
1.5
15
65 kHz < f < 1.3 MHz
300 Hz < f < 6.5 kHz
10 Hz < f < 30 Hz
Sinusoidal
Input Jitter
22
15
Amplitude
(UI p-p)
1.5
0.15
f0
f2
f3
ft
f1
Frequency
OC/STS
Level
f0
(Hz)
f1
(Hz)
f2
(Hz)
f3
(kHz)
ft
(kHz)
12
3
10
10
30
30
300
300
25
250
6.5
65
AMCC Confidential and Proprietary
DS2018
13
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
