Revision 3.03 – May 25, 2007
S1220 – SONET/SDH/ATM Quad OC-3/12
with Clock Data Recovery (CDR)
Advance Data Sheet
The S1220 is divided into four clock recovery modules.
Each of the modules can run at OC-3 or OC-12 data
rates, independent from the other modules.
S1220 OVERVIEW
The quad S1220 supports clock and data recovery for
the OC-3 or OC-12 data rates. The differential serial
data is input to the chip and clock recovery is per-
formed on the incoming data stream. An external
reference clock is required to establish the initial oper-
ating frequency of the clock recovery PLL and provide
a stable output clock source in the absence of serial
input data. Recovered clock and retimed data are out-
put by the S1220.
The sequence of operations is as follows:
•
•
•
Serial input data
Serial clock and data recovery
Serial clock and data outputs
Table 1. Suggested Interface Devices
AMCC
AMCC
AMCC
S4805
DANUBE
SONET/SDH Mapper STS-48/STM-16, 4 x STS-12/STM-4 x STS-3/STM-1
0C-48/4 x OC-12 SONET/SDH Framer and channelized ATM/POS Mapper
STS-12/STM-4 DS3/E3/DS1 E1/VT/TU SONET/SDH Mapper
SFF Optical Transceiver
S4806
OHIO
S1208
EVROS
Agilent
Finisar
HFBR-5908E
FTRJ1322P1xTR
V23818-H18
SFP Optical Transceiver
SFF Optical Transceiver
Sumitomo
SCP6802-GL
SCM6005
SFP Optical Transceiver
SFF Optical Transceiver
OCP
TRPN03 & TRPN12
CT2-P
SFP Optical Transceiver
SFP Optical Transceiver
JDS Uniphase
Table 2. Standards Compliance List
Standard
GR-253-CORE
Revision
V 3.0
Date
September 2000
GR-253-ILR- SONET Jitter Specifications
ESD – JEDEC standard: JESD22-A114-B
T1.105.03 - Standards Committee Telecommunications
ITU-T: G783 (Corrigendum 1:03/2001)
Issue 3A
Rev B
October 2000
June 2000
2002
January 2000
Note: Standards compliance only relates to applicable sections pertaining to this product type.
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