S1220 – SONET/SDH/ATM Quad OC-3/12
with Clock Data Recovery (CDR)
Figure 3. Functional Block Diagram, MII Mode
PLL CLOCK
Synthesizer
Revision 3.03 – May 25, 2007
Advance Data Sheet
TSCLKP/N
TXLOCK
REFCLK
SD0
*
LCKREFN0
REFCKINP
REFCKINN
REFCLK
LOCKDET0
PLL CLOCK
BITCLK
RECOVERY
D
Q
QN
SERDATIP0
SERDATIN0
*
RATESEL[0]
SERDATOP0
SERDATON0
*
COREOFF0
REFSEL1
REFSEL0
SD1
SERCLKOP0
SERCLKON0
0 0
0 1
1 X
*
LCKREFN1
19.44 MHz
77.76 MHz
155.52 MHz
Div
155CK0
LOCKDET1
REFCLK
SERDATIP1
SERDATIN1
*
RATESEL[1]
PLL CLOCK
BITCLK
RECOVERY
D
Q
QN
SERDATOP1
SERDATON1
MODE 1
MODE 0
*
COREOFF1
SD2
SERCLKOP1
SERCLKON1
0 0
1 1
1 0
0 1
MII Mode
NON-MII Mode
Factory TEST
Mode
Internal Mode
*
LCKREFN2
REFCLK
PLL CLOCK
BITCLK
RECOVERY
Div
155CK1
LOCKDET2
SERDATIP2
SERDATIN2
*
RATESEL[2]
D
Q
QN
SERDATOP2
SERDATON2
*
COREOFF2
SD3
SERCLKOP2
SERCLKON2
*
LCKREFN3
REFCLK
PLL CLOCK
BITCLK
RECOVERY
Div
155CK2
LOCKDET3
SERDATIP3
SERDATIN3
*
RATESEL[3]
D
Q
QN
SERDATOP3
SERDATON3
*
COREOFF3
RSTB
MDC
MDIO
MII_ADDR[0:4]
MII Register
*
Div
SERCLKOP3
SERCLKON3
155CK3
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DS2018
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
