Revision 3.03 – May 25, 2007
S1220 – SONET/SDH/ATM Quad OC-3/12
with Clock Data Recovery (CDR)
Advance Data Sheet
Figure 22. Differential LVDS Output to LVDS Input AC Coupled Termination
1.8 V
2.5 V
3.3 V
2.5 V
3.3 V
VDD
0.1 µF
0.1 µF
Zo = 50 Ω
Zo = 50 Ω
50 Ω
50 Ω
SERDES
LVDS
with Internal
Termination & Biasing
S1220
SERDATOP/N
SERCLKOP/N
LVDS
Figure 23. Differential LVPECL Output to Differential LVPECL Input AC Coupled Termination (Internal Biased)
3.3 V
3.3V
VDD
0.1
0.1
µF
Zo = 50 Ω
50 Ω
50 Ω
Zo = 50 Ω
µF
LVPECL Input
With Internal
Termination &
Biasing
S1220
SERDATOP/N
LVPECL
Note: Normally AC coupling is not required for the LVPECL interface. If the interface is not compliant for the DC voltage level, then this ter-
mination will apply.
Figure 24. Differential LVPECL Output to Differential LVPECL Input AC Coupled Termination (Not internal Biased)
VDD
3.3 V
3.3V
VDD-1.3V
82 Ω
0.1 µF
0.1 µF
Zo = 50 Ω
Zo = 50 Ω
VDD
82 Ω
130Ω
130Ω
LVPECL Input
Without Internal
Termination &
Biasing
S1220
SERDATOP/N
LVPECL
Note: Normally AC coupling is not required for the LVPECL interface. If the interface is not compliant for the DC voltage level, then this ter-
mination will apply.
40
DS2018
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
