Revision 3.03 – May 25, 2007
S1220 – SONET/SDH/ATM Quad OC-3/12
with Clock Data Recovery (CDR)
Advance Data Sheet
RECOMMENDED TERMINATIONS
Figure 17. Differential LVPECL Output to Differential LVPECL Input DC Coupled Termination
DCBIAS = 1
3.3 V
VDDH = 3.3 V
VDDI
Zo = 50 Ω
P
Ω
Ω
50
50
N
Zo = 50 Ω
150Ω
150Ω
150Ω
150Ω
LVPECL
Ouput Driver
These pull down resistors have
been moved inside the S1220
Inputs. These resistors biasing can
enabled and disabled via
DCBIAS pin
S1220
SERDATIP/N
LVPECL
DCBIAS = 1
Figure 18. Differential LVPECL Output to Differential LVPECL Input AC Coupled Termination VDDH = 3.3 V
VDDH = 3.3 V
VDDI
0.1 µF
150 - 300 Ω
150 - 300
Zo = 50 Ω
Zo = 50 Ω
50 Ω
50 Ω
Ω
0.1 µF
S1220
SERDATIP/N
LVPECL
DCBIAS = 0
LVPECL
Note: Normally AC coupling is not required for the LVPECL interface. If the interface is not compliant for the DC voltage level, then this ter-
mination will apply
38
DS2018
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