Part Number S1220
Revision 3.03 – May 25, 2007
S1220
FEATURES
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CMOS 0.13 micron technology
Complies with Bellcore and ITU-T specifica-
tions for jitter tolerance, jitter transfer, and jitter
generation
On-chip high-frequency PLLs for clock genera-
tion and clock recovery
Supports clock recovery for 155.52 Mbps
(OC-3) and 622.08 Mbps (OC-12)
Selectable reference frequencies of 19.44,
77.76 or 155.52 MHz
Directly compatible with 2.5 V or 3.3 V LVDS,
3.3 V LVPECL (DC and AC coupling)
196 PBGA Package with Green/RoHS compli-
ant lead free option
1.2 V and 3.3 V/2.5 V supply
Lock detect
Signal detect input (SD[3:0])
Typical 320 mW power in LVDS mode
Internal termination to the OPTICs LVPECL
driver rendering seamless connection and sav-
ing power at the system level
Quad configuration, mixed OC-3/OC-12
S1220 is a drop-in replacement for S1212
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Advance Data Sheet
APPLICATIONS
SONET/SDH OC-3/OC-12
SONET/SDH/ATM Quad OC-3/12 with Clock Data Recovery (CDR)
GENERAL DESCRIPTION
The function of the S1220 clock and data recovery unit
is to derive high speed timing signals for SONET/SDH-
based equipment. The S1220 receives either an OC-3
or OC-12 scrambled NRZ signal and recovers the
clock from the data. The chip outputs a differential bit
clock and retimed data. Figure 1 shows a typical net-
work application.
The S1220 utilizes five on-chip PLLs which consist of
a phase detector, a loop filter, and a voltage controlled
oscillator (VCO). The phase detector compares the
phase relationship between the VCO output and the
serial data input. A loop filter converts the phase
detector output into a smooth DC voltage, and the DC
voltage is input to the VCO whose frequency is varied
by this voltage. The S1220 can also be provisioned as
a mix between OC-3 and OC-12 data. Detailed block
diagrams are shown in Figure 2 and Figure 3. The
S1220 is packaged in a 196 PBGA, offering designers
a small package outline (see Figure 9).
The S1220 can be configured in MII (Media Indepen-
dent Interface) mode (CDR with MII interface) and in
non-MII mode (CDR without MII interface).
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Figure 1. System Block Diagram
OTX
ORX
DATA
CDR
DATA
CDR
CLOCK
CDR
DATA
CDR
CLOCK
DATA
ORX
OTX
CDR
DATA
CDR
CLOCK
CDR
DATA
CDR
CLOCK
DATA
OTX
ORX
Framers
With Integrated
SERDES
Or
ASIC
DATA
ORX
OTX
S1220
CDR
DATA
CDR
CLOCK
CDR
DATA
CDR
CLOCK
OTX
ORX
S1220
DATA
CDR
DATA
CDR
CLOCK
CDR
DATA
CDR
CLOCK
Framer
With integrated
SERDES
Or
ASIC
DATA
ORX
OTX
OTX
ORX
DATA
DATA
ORX
OTX
MII port
MII port
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DS2018
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
