Revision 3.03 – May 25, 2007
S1220 – SONET/SDH/ATM Quad OC-3/12
with Clock Data Recovery (CDR)
Advance Data Sheet
In both LVDS and LVPECL formats the S1220 sets the
common mode internally. No external biasing is
MODES OF OPERATION
1. Non-MII Mode: (Mode[1:0] = 11) CDR without MII
required. Only 100
Ω between the P/N on the end of
programing
the input transmission line is required.
2. MII Mode: (Mode[1:0] = 00) CDR with MII pro-
graming
The serial input format (Serial Data and Reference
clock) can be AC or DC coupled.
Non-MII enables use of the S1220 without the need of
a micro controller to program the MII register file.
MII mode enables access to a wider set of control
options.
When the serial input is in LVPECL format, the S1220
provides an optional internal DC biasing feature for the
LVPECL drivers. Using this feature results in board
level power saving of the Optics 3.3 V supply, and pro-
vides seamless connection without external
components (See Figure 17).
The serial output format (Serial data and Clocks) can
be either LVDS (with VDDH supply voltage 3.3V or
2.5V) or LVPECL (with VDDH supply voltage 3.3V).
See Table 4, Serial I/O Modes of Operation in MII
Mode.
Table 4. Serial I/O Modes of Operation
Controls Bits in
MII mode
Controls Pins in
Non-MII mode
VDDH
In/Out
I/O Mode
LVDS DC
3.3 V/2.5 V Serial Data input
3.3 V/2.5 V Reference clock input
3.3 V/2.5 V Serial Data output &
XDCBIAS=0
XACEN=0
DCBIAS=0
Internal bias on. DC driver overrides
LVDS AC
XDCBIAS=0
XACEN=1
DCBIAS=0
Internal bias on
LVPECL DC
Without external biasing
XDCBIAS=1
XACEN=0
DCBIAS=1
Internal bias on. DC driver overrides
LVPECL DC
With external biasing
XDCBIAS=0
XACEN=0
DCBIAS=0
Internal bias on. DC driver overrides
LVPECL AC
LVDS DC
LVDS AC
XDCBIAS=0
XACEN=1
DCBIAS=0
Internal bias on
CDCBIAS=0
CACEN=0
DCBIAS=0
Internal bias on. DC driver overrides
CDCBIAS=0
CACEN=1
DCBIAS=0
Internal bias on
LVPECL DC
Without external biasing
CDCBIAS=1
CACEN=0
DCBIAS=1
Internal bias on. DC driver overrides
LVPECL DC
With external biasing
CDCBIAS=0
CACEN=0
DCBIAS=0
Internal bias on. DC driver overrides
LVPECL AC
LVDS
CDCBIAS=0
CACEN=1
DCBIAS=0
Internal bias on
XLVDSPECLBa=1
XLVDSPECLB=0
CLVDSPECLB=1
CLVDSPECLB=0
XLVDSPECLB=1
Serial Clock output
3.3 V
LVPECL
LVDS
XLVDSPECLB=0
CLVDSPECLB=1
CLVDSPECLB=0
3.3 V/2.5 V TSCLK output
3.3 V
LVPECL
a. XLVDSPECLB pin function is on MDIO pin in Non-MII Mode
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