Revision 3.03 – May 25, 2007
S1220 – SONET/SDH/ATM Quad OC-3/12
with Clock Data Recovery (CDR)
Advance Data Sheet
Figure 25. 3.3 V Differential LVPECL Oscillator to Reference Clock Input AC Coupled Termination
DCBIAS = 0
3.3 V
VDDH = + 3.3 V
VDDI
0.1 µF
0.1 µF
Zo = 50 Ω
P
50 Ω
50 Ω
300 Ω
300 Ω
N
Zo = 50 Ω
Ω
Ω
150
150
OSCILLATOR
LVPECL
S1220
REFCLKP/N
LVPECL
Figure 26. 3.3 V Differential LVPECL Oscillator to Reference Clock Input DC Coupled Termination
DCBIAS = 1
3.3 V
VDDH = + 3.3 V
VDDI
Zo = 50 Ω
Zo = 50 Ω
P
50 Ω
50 Ω
N
Ω
150
150 Ω
These pull down resistors have
been moved inside the S1220
Inputs. These resistors biasing can
be enabled and disabled via
DCBIAS pin
S1220
REFCLKP/N
LVPECL
OSCILLATOR
LVPECL
DCBIAS = 1
Figure 27. Differential LVDS Output to Differential LVDS Input AC Coupled Termination
2.5 V
3.3 V
1.8 V
55 k
1.8 V
55 k
1.8 V
Ω
0.1 µF
0.1 µF
Ω
Zo = 50 Ω
Zo = 50 Ω
1.25V 125 kΩ
125 kΩ
S1220
LVDS Input
Without Internal
Termination &
Biasing
SERDATOP/N
LVDS
Note: Normally AC coupling is not required for the LVDS interface. If the interface is not compliant to the LVDS DC voltage level and the
inputs are not biased and terminated internally, then this termination will apply.
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DS2018
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
