SPRS174S – APRIL 2001 – REVISED MARCH 2011
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6.31.2 McBSP as SPI Master or Slave Timing
Table 6-52. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
(1)
NO.
M30
M31
M32
M33
(1)
t
su(DRV-CKXL)
t
h(CKXL-DRV)
t
su(BFXL-CKXH)
t
c(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX high
Cycle time, CLKX
2P
MASTER
MIN
30
1
MAX
SLAVE
MIN
8P – 10
8P – 10
8P + 10
16P
MAX
UNIT
ns
ns
ns
ns
2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
Table 6-53. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
(1)
NO.
M24
M25
M28
M29
(1)
t
h(CKXL-FXL)
t
d(FXL-CKXH)
t
dis(FXH-DXHZ)
t
d(FXL-DXV)
PARAMETER
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
Disable time, DX high impedance following last data bit
from FSX high
Delay time, FSX low to DX valid
MASTER
MIN
2P
P
6
6
6P + 6
4P + 6
MAX
SLAVE
MIN
MAX
UNIT
ns
ns
ns
ns
2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
LSB
M32
MSB
M33
CLKX
M24
FSX
M28
DX
Bit 0
M30
DR
Bit 0
Bit(n-1)
M29
Bit(n-1)
(n-2)
M31
(n-2)
(n-3)
(n-4)
(n-3)
(n-4)
M25
Figure 6-45. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
152
Electrical Specifications
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