SPRS174S – APRIL 2001 – REVISED MARCH 2011
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
SPISOMI
Master In Data
Must Be Valid
SPISTE
(A)
A.
In the master mode, SPISTE goes active 0.5t
c(SPC)
before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5t
c(SPC)
after the receiving
edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 6-26. SPI Master Mode External Timing (Clock Phase = 0)
118
Electrical Specifications
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