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SPRS174S – APRIL 2001 – REVISED MARCH 2011
Table 6-54. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
(1)
NO.
M39
M40
M41
M42
(1)
t
su(DRV-CKXH)
t
h(CKXH-DRV)
t
su(FXL-CKXH)
t
c(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX high
Cycle time, CLKX
2P
MASTER
MIN
30
1
MAX
SLAVE
MIN
8P – 10
8P – 10
16P + 10
16P
MAX
UNIT
ns
ns
ns
ns
2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
Table 6-55. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
(1)
NO.
M34
M35
M37
M38
(1)
t
h(CKXL-FXL)
t
d(FXL-CKXH)
t
dis(CKXL-DXHZ)
t
d(FXL-DXV)
PARAMETER
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
Disable time, DX high impedance following last data bit
from CLKX low
Delay time, FSX low to DX valid
MASTER
MIN
P
2P
P+6
6
7P + 6
4P + 6
MAX
SLAVE
MIN
MAX
UNIT
ns
ns
ns
ns
2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
LSB
CLKX
M34
FSX
M37
DX
Bit 0
M39
DR
Bit 0
Bit(n-1)
M38
Bit(n-1)
(n-2)
M40
(n-2)
(n-3)
(n-4)
(n-3)
(n-4)
M35
MSB
M42
M41
Figure 6-46. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
Copyright © 2001–2011, Texas Instruments Incorporated
Electrical Specifications
153
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