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SPRS174S – APRIL 2001 – REVISED MARCH 2011
M1, M11
M2, M12
M3, M12
CLKR
M4
FSR (int)
M15
FSR (ext)
M18
M17
DR
(RDATDLY=00b)
DR
(RDATDLY=01b)
DR
(RDATDLY=10b)
Bit (n-1)
M17
Bit (n-1)
M17
Bit (n-1)
(n-2)
M18
(n-2)
M18
(n-2)
(n-3)
(n-3)
(n-4)
M16
M4
M14
M13
Figure 6-43. McBSP Receive Timing
M1, M11
M2, M12
M3, M12
CLKX
M5
FSX (int)
M19
FSX (ext)
M9
DX
(XDATDLY=00b)
M10
Bit 0
Bit (n-1)
M8
DX
(XDATDLY=01b)
Bit 0
M6
DX
(XDATDLY=10b)
M8
Bit 0
Bit (n-1)
(n-2)
Bit (n-1)
(n-2)
M7
(n-3)
(n-2)
M7
M7
(n-3)
(n-4)
M20
M5
M13
M14
Figure 6-44. McBSP Transmit Timing
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Electrical Specifications
151
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