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TMS320F2812PGFS 参数 Datasheet PDF下载

TMS320F2812PGFS图片预览
型号: TMS320F2812PGFS
PDF下载: 下载PDF文件 查看货源
内容描述: 数字信号处理器 [Digital Signal Processors]
分类和应用: 数字信号处理器
文件页数/大小: 170 页 / 1662 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SPRS174S – APRIL 2001 – REVISED MARCH 2011
6.30.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels
(A0/B0 to A7/B7). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB),
software trigger, or from an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions
on two selected channels on every Sample/Hold pulse. The conversion time and latency of the Result
register update are explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the
Result register update. The selected channels will be sampled simultaneously at the falling edge of the
Sample/Hold pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum)
or 16 ADC clocks wide (maximum).
NOTE
In Simultaneous Mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7,
and
not
in other combinations (such as A1/B3, etc.).
Sample n
Analog Input on
Channel Ax
Analog Input on
Channel Bv
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
ADC Event Trigger from EV
or Other Sources
t
SH
Sample n+1
Sample n+2
t
d(SH)
t
dschA0_n+1
t
dschA0_n
t
dschB0_n
t
dschB0_n+1
Figure 6-42. Simultaneous Sampling Mode Timing
Table 6-49. Simultaneous Sampling Mode Timing
SAMPLE n
t
d(SH)
t
SH
t
d(schA0_n)
Delay time from event
trigger to sampling
Sample/Hold width/
Acquisition Width
Delay time for first
result to appear in
Result register
Delay time for first
result to appear in
Result register
Delay time for
successive results to
appear in Result
register
Delay time for
successive results to
appear in Result
register
2.5t
c(ADCCLK)
(1 + Acqps) * t
c(ADCCLK)
4t
c(ADCCLK)
40 ns with Acqps = 0
160 ns
Acqps value = 0–15
ADCTRL1[8:11]
SAMPLE n + 1
AT 25-MHz
ADC CLOCK,
t
c(ADCCLK)
= 40 ns
REMARKS
t
d(schB0_n)
5t
c(ADCCLK)
200 ns
t
d(schA0_n+1)
(3 + Acqps) * t
c(ADCCLK)
120 ns
t
d(schB0_n+1)
(3 + Acqps) * t
c(ADCCLK)
120 ns
Copyright © 2001–2011, Texas Instruments Incorporated
Electrical Specifications
147
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