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SPRS174S – APRIL 2001 – REVISED MARCH 2011
Table 6-43. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
(1) (2) (3)
MIN
t
d(HL-HiZ)
t
d(HL-HAL)
t
d(HH-HAH)
t
d(HH-BV)
(1)
(2)
(3)
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
Delay time, XHOLD low to XHOLDA low
Delay time, XHOLD high to XHOLDA high
Delay time, XHOLD high to Bus valid
MAX
4t
c(XTIM)
+ t
c(XCO)
4t
c(XTIM)
+ 2t
c(XCO)
4t
c(XTIM)
6t
c(XTIM)
UNIT
ns
ns
ns
ns
When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
The state of XHOLD is latched on the rising edge of XTIMCLK.
After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions will occur with respect to the rising edge of
XCLKOUT. Thus, for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the
maximum value specified.
XCLKOUT
(1/2 XTIMCLK)
t
d(HL-HAL)
XHOLD
t
d(HH-HAH)
XHOLDA
t
d(HL-HiZ)
t
d(HH-BV)
High-Impedance
XR/W,
XZCS0AND1,
XZCS2,
XZCS6AND7
XA[18:0]
Valid
High-Impedance
Valid
XD[15:0]
See Note (A)
Valid
High-Impedance
See Note (B)
A.
B.
All pending XINTF accesses are completed.
Normal XINTF operation resumes.
Figure 6-38. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
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Electrical Specifications
141
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