SPRS174S – APRIL 2001 – REVISED MARCH 2011
www.ti.com
6.30.6 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax
to Bx). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software
trigger, or from an external ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the
selected channel on every Sample/Hold pulse. The conversion time and latency of the Result register
update are explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result
register update. The selected channels will be sampled at every falling edge of the Sample/Hold pulse.
The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks
wide (maximum).
Sample n+2
Sample n+1
Analog Input on
Channel Ax or Bx
Sample n
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
t
d(SH)
t
dschx_n
ADC Event Trigger from EV
or Other Sources
t
SH
t
dschx_n+1
Figure 6-41. Sequential Sampling Mode (Single-Channel) Timing
Table 6-48. Sequential Sampling Mode Timing
SAMPLE n
t
d(SH)
t
SH
Delay time from event
trigger to sampling
Sample/
Hold width/
Acquisition width
Delay time for first
result to appear in the
Result register
Delay time for
successive results to
appear in the Result
register
2.5t
c(ADCCLK)
(1 + Acqps) * t
c(ADCCLK)
40 ns with Acqps = 0
Acqps value = 0–15
ADCTRL1[8:11]
SAMPLE n + 1
AT 25-MHz
ADC CLOCK,
t
c(ADCCLK)
= 40 ns
REMARKS
t
d(schx_n)
4t
c(ADCCLK)
160 ns
t
d(schx_n+1)
(2 + Acqps) * t
c(ADCCLK)
80 ns
146
Electrical Specifications
Copyright © 2001–2011, Texas Instruments Incorporated
Product Folder Link(s):
TI [ TEXAS INSTRUMENTS ]
