SPRS174S – APRIL 2001 – REVISED MARCH 2011
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12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
18
SPISOMI
SPISOMI Data Is Valid
21
22
SPISIMO
SPISIMO Data
Must Be Valid
Data Valid
SPISTE
(A)
A.
In the slave mode, the SPISTE signal should be asserted low at least 0.5t
c(SPC)
before the valid SPI clock edge and
remain low for at least 0.5t
c(SPC)
after the receiving edge (SPICLK) of the last data bit.
Figure 6-29. SPI Slave Mode External Timing (Clock Phase = 1)
124
Electrical Specifications
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