SPRS174S – APRIL 2001 – REVISED MARCH 2011
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See
Notes (A)
and (B)
Lead 1
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
XRD
t
d(XCOH-XZCSL)
t
d(XCOH-XA)
WS (Async)
Active
Trail
See Note (C)
t
d(XCOHL-XZCSH)
t
h(XRDYasynchH)XZCSH
t
d(XCOHL-XWEL)
XWE
t
d(XCOH-XRNWL)
XR/W
t
d(XWEL-XD)
t
en(XD)XWEL
XD[0:15]
DOUT
t
su(XRDYasynchL)XCOHL
t
h(XRDYasynchL)
t
e(XRDYasynchH)
t
su(XRDYasynchH)XCOHL
XREADY(Asynch)
See Note (D)
See Note (E)
Legend:
= Don’t care. Signal can be high or low during this time.
t
d(XCOHL-XWEH)
t
d(XCOHL-XRNWH)
t
dis(XD)XRNW
t
h(XD)XWEH
A.
B.
C.
D.
E.
All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
During alignment cycles, all signals will transition to their inactive state.
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE – 3 + n) t
c(XTIM)
– t
su(XRDYasynchL)XCOHL
where n is the sample number (n = 1, 2, 3 and so forth).
Reference for the first sample is with respect to this point
E = (XWRLEAD + XWRACTIVE – 2) t
c(XTIM)
Figure 6-36. Write With Asynchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
N/A
(1)
(1)
XRDACTIVE
N/A
(1)
XRDTRAIL
N/A
(1)
USEREADY
1
X2TIMING
0
XWRLEAD
≥
1
XWRACTIVE
3
XWRTRAIL
≥
1
READYMODE
1 = XREADY
(Async)
N/A = “Don’t care” for this example
138
Electrical Specifications
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