VS1005g Datasheet
10 VS1005 PERIPHERALS AND REGISTERS
master generates the clock and sync signals.
I2S_CF_ENAMCK is the 12 MHz output clock enable signal. It can be used to clock external
I2S circuitry. This clock is the same clock as the xtal oscillator clock of vs1005.
I2S_CF_ENA is the transmitter and receiver enable signal. When set the receiver and trans-
mitter enter the active state.
I2S_CF_FS register is used to set the I2S peripheral sample rate. This register can be modified
only when I2S is in idle state, i.e. I2S_CF_ENA is reset. Next table lists the sample rates when
12.288 MHz xtal is used.
I2S Sample Rates
I2S_CF_FS[1:0] 16-bit mode 32-bit mode
11
10
01
00
48kHz
192kHz
96kHz
48kHz
24kHz
96kHz
48kHz
24kHz
I2S_CF_MODE register selects between dsp mode and SRC mode. In dsp mode the data is
transferred from left and right data registers. In SRC mode the data is sampled from DAC’s
SRC filter and I2S is operating in master mode only.
I2S_CF_TXURUN is the transmitter under run flag register. It is set if left or right data buffer
register was empty as it was copied to shifter register.
I2S_CF_TXLFULL and I2S_CF_TXRFULL registers are the transmitter data buffer full flags for
left and right channel. Flags are set when transmitter data buffer registers are modified. The
flags are reset as the left and right data buffer is copied to shifter register.
I2S_CF_RXORUN is the receiver over run flag. It is set when receiver data buffers were full
and new frame was received. The flag is reset by writing it to ’0’.
I2S_CF_RXLFULL and I2S_CF_RXRFULL are the receiver data buffer full flags for left and
right channel. Flags are set when receiver data buffer registers are full. The flags are reset as
the left and right data buffer is read.
I2S_CF_INTENA enables the I2S interrupt when set.
I2S_CF_32B register selects between 32-bit (1) and 16-bit (0) data format. This register can
be modified only in idle state.
I2S_LEFT, I2S_LEFT_LSB, I2S_RIGHT and I2S_RIGHT_LSB are the left and right data reg-
isters for receiver and transmitter. Each write to I2S_LEFT and I2S_RIGHT registers sets the
I2S_CF_TXLFULL and I2S_CF_TXRFULL flags. Each read from I2S_LEFT and I2S_RIGHT
registers resets the I2S_CF_RXLFULL and I2S_CF_RXRFULL flags. In 16-bit mode the reg-
isters I2S_LEFT_LSB and I2S_RIGHT_LSB are not used. In 32-bit mode they are used to
transfer 16-lsb bits of data.
Version: 0.2, 2012-03-16
91
ETC [ ETC ]
