VS1005g Datasheet
10 VS1005 PERIPHERALS AND REGISTERS
FM_CF Bits
Name
Bits Description
FM_CF_UAD2
FM_CF_UAD1
FM_CF_UAD3
14 AD2 input selection
13 AD1 input selection
12 AD3 input selection
11:8 Reserved, Use “000”
FM_CF_PHCOMP
FM_CF_INIT
7
6
Enable for FM I- and Q- signal scaling
Software reset for AD filters and FM demodu-
lator
FM_CF_RDSSYNC
FM_CF_MONO
FM_CF_DEEMP
5
4
3
FM RDS forced to keep synchronization
FM receiver mono (1) / stereo (0) selection
FM de-emphasis filter configuration 75µs or
50µs
FM_CF_RDSENA
FM_CF_CCFLCK
FM_CF_FMENA
2
1
0
FM RDS enable
FM carrier lock enable
FM demodulator enable
In FM mode the registers FM_CF_UAD2 and FM_CF_UAD1 must be reset.
FM_CF_PHCOMP is the enable signal for FM input scaling.
FM_CF_INIT is the global enable for FM demodulator and AD filters. This signal can also be
used to resynchronize the mono/stereo AD filters. Logic is enabled when this register is set.
FM_CF_RDSSYNC forces the RDS decoder to keep current symbol synchronization. When
sync search is enabled (i.e. FM_CF_RDSSYNC is reset) the RDS decoder tries to find best
symbol synchronization at all times, even when the FM signal is lost.
FM_CF_MONO register selects between mono and stereo receive modes. When set the mode
is mono.
FM_CF_DEEMP register selects between 75µs (North America) or 50µs (Europe, Australia)
de-emphasis filters. When set the de-emphasis is 75µs.
FM_CF_RDSENA register enables the rds calculation logic when set.
FM_CF_CCFLCK register enables automatic FM fine tuning when set. When reset the FM
band frequency is always at fixed value (as defined in FMCCF register).
FM_CF_FMENA is the FM demodulator enable. The register must be set when FM is used.
To receive in stereo mode the FM_PLL registers must be initialized correctly. These regis-
ters (FMPLL_HI and FMPLL_LO) set the FM stereo carrier PLL frequency. This factor is xtal
dependent and is defined as:
(64×228×38000Hz)
pll_factor =
XTAL_freqHz
Version: 0.2, 2012-03-16
87
ETC [ ETC ]
