VS1005g Datasheet
10 VS1005 PERIPHERALS AND REGISTERS
10.18 I2S Peripheral
Vs1005 has a bi-directional I2S digital interface. I2s is a serial audio interface which uses serial
bit clock (i2s_bck), frame sync (i2s_frm) and serial data line (i2s_dout, i2s_din) to transfer data.
I2s frame consists of left and right data which is transmitted left word first and MSB bit first.
Data is latched out at falling edge of bit clock and latched in at rising edge of bit clock. I2s data
format is shown in Figure 20.
Figure 20: I2s Frame format.
10.18.1 I2S Peripheral Registers
I2S Registers
Reg Type Reset Abbrev
Description
0xFE60
0xFE61
0xFE62
0xFE63
0xFE64
r/w
r/w
r/w
r/w
r/w
0
0
0
0
0
I2S_CF[13:0]
I2S_LEFT_LSB
I2S_LEFT
I2S_RIGHT_LSB Right data bits[15:0]
I2S_RIGHT Right data bits[32:16]
Configuration and status register
Left data bits[15:0]
Left data bits[32:16]
I2S_CF Bits
Bits Description
Name
I2S_CF_32B
13 32-bit mode (1) / 16-bit mode (0) select
12 I2S peripheral interrupt enable
11 Receiver right data register full
10 Receiver left data register full
I2S_CF_INTENA
I2S_CF_RXRFULL
I2S_CF_RXLFULL
I2S_CF_RXORUN
I2S_CF_TXRFULL
I2S_CF_TXLFULL
I2S_CF_TXURUN
I2S_CF_MODE
9
8
7
6
5
Receiver over run flag
Transmitter right data register full
Transmitter left data register full
Transmitter under run flag
I2S peripheral mode select (dsp or SRC out)
I2S_CF_FS[1:0]
I2S_CF_ENA
I2S_CF_ENAMCK
I2S_CF_MASTER
4:3 I2S sample rate selection
2
1
0
I2S peripheral enable
I2S master clock (12 MHz) pad driver enable
I2S master (1) / slave (0) mode select
I2S_CF_MASTER bit is used to select between master (1) and slave (0) modes. In master
mode the vs1005 generates bit clock and frame sync signals. In slave mode the external I2S
Version: 0.2, 2012-03-16
90
ETC [ ETC ]
