Ver 1.3
PRELIMINARY
EAGLE
3.22.2.10 USB MAXP Register (USBMP)
Address : 0xFFE0_9828h
Bit
31 : 8
7 : 0
R/W
R
R/W
Description
Default Value
Reserved
-
Max FIFO Size
0000_0000
0000_0010
0000_0100
0000_1000
00h
MAXP=8
MAXP=16
MAXP=32
MAXP=64
3.22.2.11 USB EP0 Control Register (USBEP0CON)
Address : 0xFFE0_982Ch
R/W
MCU USB
Default
Value
-
Bit
Description
31 : 8
7
R
Reserved
Clear
EP0SUEC : EP0 Set Up End Clear bit.
MCU clears EP0STED bit by writing a ‘1’ to this bit.
EP0OPRC : EP0 Out Packet Ready Clear bit.
MCU clears EP0OPR bit by writing a ‘1’ to this bit.
Clear EP0SDSTAL : EP0 Send Stall bit.
If MCU recognizes a wrong token, it clears EP0OPR bit and
set this bit.
0b
6
5
Clear
Set
0b
0b
USB generates STALL handshake for current control transfer.
MCU writes ‘0’ to terminate STALL status.
4
3
R
Set
EP0STED : EP0 Setup End bit. This bit is read only.
If control transfer is terminated before EP0DED bit is set, USB
sets this bit.
When USB sets this bit, interrupt is generated to MCU.
When this scenario occurs, USB flushes FIFO, ignores MCU
access to FIFO and, clears this bit.
0b
0b
Set/R Clear EP0DED : EP0 Data End bit.
MCU sets this when the following conditions are met.
-
-
-
After MCU loads the data packet to FIFO, both this bit
and EP0IPR bit are set simultaneously.
When clearing EP0OPR bit after the last packet is
fetched.
When clearing EP0OPR bit and setting EP0IPR bit for
zero length data.
2
1
Clear/
R
Set
EP0STSTAL : Sent Stall bit.
USB sets this bit when control transaction is terminated due to
protocol error. If this bit is set, USB will issue an interrupt.
0b
0b
Set/R Clear EP0IPR : EP0 In Packet Ready bit.
MCU sets this bit after writing the data packet to endpoint 0
FIFO.
If the data packet is successfully transferred to host, USB
clears this bit.
If USB clears this bit, interrupt will be generated to inform
MCU to load the next data.
For zero length data phase, MCU sets this bit (EP0IPR) and
EP0DED bit simultaneously.
0
R
Set
EP0OPR : EP0 Out Packet Ready bit.
This is a read-only bit.
0b
If a valid token is written into FIFO, USB sets this bit and
interrupt is generated. MCU clears this bit by writing a ‘1’ to
EP0OPRC bit
179
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Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
