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PKM32AG-Q 参数 Datasheet PDF下载

PKM32AG-Q图片预览
型号: PKM32AG-Q
PDF下载: 下载PDF文件 查看货源
内容描述: EAGLE是一款多媒体处理器.EAGLE集成了带有DSP特性的32位EISC CPU处理器、H.264解码器、JPEG解码器、2D图像引擎、声音混音器、具有OSD功能的CRT控制器、视频编码器、视频解码接口模块、USB主/从和通用I/O外设接口。 [EAGLE是一款多媒体处理器。EAGLE集成了带有DSP特性的32位EISC CPU处理器、H.264解码器、JPEG解码器、2D图像引擎、声音混音器、具有OSD功能的CRT控制器、视频编码器、视频解码接口模块、USB主/从和通用I/O外设接口。]
分类和应用: 解码器编码器控制器
文件页数/大小: 235 页 / 4257 K
品牌: ETC [ ETC ]
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Ver 1.3  
PRELIMINARY  
EAGLE  
3.22.2.14 USB OUT Control Register 1 (USBOCON1)  
Address : 0xFFE0_9838h  
R/W  
MCU  
R
Default  
Value  
Bit  
Description  
USB  
31 : 8  
7
Reserved  
-
0b  
R/W  
R
OCCDT : Out Control 1 Clear Data Toggle bit.  
When MCU writes ‘1’ to this bit, data toggle sequence bit is  
reset to DATA0.  
6
Clear/R  
Set  
R
OCSTSTAL : Out Control 1 Sent Stall bit.  
USB sets this bit when OUT token is terminated due to a  
STALL handshake,.  
When data packet in an OUT token is bigger than MAXP data,  
USB generates a stall handshake to host.  
MCU clears this bit by writing a ‘0’.  
OCSDSTAL : Out Control 1 Send Stall bit.  
MCU sets this bit to ‘1’ and a STALL handshake is generated  
to USB. To terminate the STALL status, MCU writes ‘0’ to  
this bit.  
0b  
5
4
3
W/R  
R/W  
R
0b  
0b  
0b  
Clear OCFFLU : Out Control 1 FIFO Flush bit.  
MCU sets this bit to ‘1’ to flush FIFO and clears this bit to stop  
the flush operation. This bit can be set if OCOPR bit is set.  
Data packet fetched by MCU will be flushed.  
R/W OCERR : Out Control 1 Data Error bit  
An error (bit stuffing or CRC) in the data packet fetched by  
MCU from FIFO will cause this bit to be set. This bit is  
automatically cleared when OCOPR bit is cleared.  
2
1
R
R
R
Reserved  
-
0b  
R/W OCFFUL : Out Control 1 FIFO Full bit.  
Indicates no more data packet can be stored.  
0 : there is available space for data storage in FIFO.  
1 : No available space for data storage in FIFO.  
0
R/  
Clear  
Set  
OCOPR : Out Control 1 Out Packet Ready bit.  
USB sets this bit when data packet is loaded into FIFO. MCU  
must clear this bit by writing a ‘0’ after it reads the entire data  
packet.  
0b  
3.22.2.15 USB OUT Control Register 2 (USBOCON2)  
Address : 0xFFE0_983Ch  
R/W  
MCU USB  
Default  
Value  
-
Bit  
Description  
31 : 8  
7
R
Reserved  
R/W  
R
OCACLR : Out Control 2 Auto Clear bit.  
When this bit is set, OCOPR bit is cleared by USB core when  
data is read from OUT FIFO  
0b  
6 : 0  
R
Reserved  
-
3.22.2.16 USB Low Byte Out Write Count Register (USBLBOWC)  
Address : 0xFFE0_9840h  
Bit  
R/W  
Description  
Default  
Value  
-
31 : 8  
7 : 0  
R
R/W  
Reserved  
(LBOWC) Low Byte OEP write count register  
00h  
181  
CONFIDENTIAL  
Beijing Peak Microtech Co.Ltd.  
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