Ver 1.3
PRELIMINARY
EAGLE
3.23
Watch Dog Timer
Watch Dog Timer resets the CPU when CPU is malfunctioning as a result of system error or noise. When Watch Dog
Timer is enabled, a 32-bit counter (WDCNT) counts down according to APB (AHB clock/2) clock, and system reset occurs
when the 32-bit counter (WDCNT) value reaches ‘0’, the system reset is executed.
When Watch Dog Timer is used, WDCNT register should be set to a value other than ‘0’ to prevent the 32-bit counter
from having a ‘0’ value. If counter is initialized to ‘0’, Watch Dog Timer would wrongly execute a CPU reset and system
would be misinterpreted as having an abnormal operation.
3.23.1 Watch Dog Timer Control Register (WDCON)
Address : FFE0 9C00h
Bit
31 : 5
4
R/W
R
R
Description
Default Value
Reserved.
-
0b
Watch Dog Reset Status. It is cleared when WDCON Read.
0 : Normal
1 : Reset occurred by Watch Dog
3 : 1
0
R
R/W
Reserved.
Watch Dog Timer Enable / Disable
0 : Disable Timer
-
0b
1 : Enable Timer
3.23.2 Watch Dog Timer Count Register (WDCNT)
Address : FFE0 9C04h
Bit
31 : 0
R/W
R/W
Description
Watch Dog Timer Count Value.
Default Value
FFFF FFFFh
Watch Dog Timer counts down from the written value. When ‘0’ is
reached, a reset is initiated. Therefore, Watch Dog Timer Count Value
must be set to a value greater than ‘0’.
This register reflects the value of the Watch Dog Counter and reading
this register would return the current counter value.
Watch Dog Reset Time
Time
1 sec
WDCNT
02FAF080h
05F5E100h
0EE6B280h
1DCD6500h
59682F00h
B2D05E00h
FFFFFFFFh
2 sec
5 sec
10 sec
30 sec
1 min
85.9 sec
Table 3-30 Watch-Dog Timer Counter Setting
* System CLOCK : 100 Mhz, APB CLOCK : 50 MHz (20 ns) reference.
183
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
