EAGLE
PRELIMINARY
Ver 1.3
3.22.2.12 USB IN Control 1 Register (USBICON1)
Address : 0xFFE0_982Ch
R/W
Default
Value
Bit
Description
MCU
R
Set
USB
31 : 7
6
Reserved
-
0b
R/Clear ICCDT : In Control 1 Clear Data Toggle bit.
MCU clears the data toggle bit by writing a ’1’ to this bit. This
bit is write only bit.
5
R/
Set
ICSTSTAL : In Control 1 Sent Stall bit.
0b
Clear
STALL handshake is generated for IN token when MCU sets
ICSDSTAL bit. USB then sets this bit. If STALL handshake is
generated, ICIPR bit will be cleared.
MCU clears this bit by writing a ‘0’ to this bit.
ICSDSTAL : In Control 1 Send Stall bit.
MCU sets this bit to ‘1’ which results in the generation of
STALL handshake.
MCU clears this bit to terminate STALL.
ICFFLU : In Control 1 FIFO Flush bit.
4
3
R/W
R
0b
0b
R/Set
Clear
MCU sets this bit in an attempt to flush IN FIFOt.
USB clears this bit when FIFO is flushed. An interrupt is
generated to MCU. If a token is in progress, USB will flush
the FIFO after the transfer completes.. If two packets have
been loaded into FIFO, the uppermost packet (packet to be sent
to host) is flushed and ICIPR bit corresponding to that packet is
cleared
2
1
R
R
Reserved
0b
0b
Set
ICFNE : In Control 1 FIFO Not Empty bit.
Indicates at least one data packet is present in FIFO.
0 : there is no data packet in FIFO.
1 : there is at least one data packet in FIFO.
0
Set /
R
Clear
ICIPR : In Control 1 In Packet Ready bit.
0b
MCU sets this bit after data packet is written to FIFO. USB
clears this bit upon the successful completion of data packet
transfer to host.
Interrupt is generated when USB clears this bit. MCU receives
the interrupt and load the next packet. When this bit is set,
MCU can not write to FIFO.
If MCU sets ICSDSTAL bit, this bit cannot be set.
3.22.2.13 USB IN Control 2 Register (USBICON2)
Address : 0xFFE0_9830h
R/W
Default
Value
-
Bit
Description
MCU
R
R/W
USB
31 : 8
7
Reserved
R
ICASET : In Control 2 Auto Set bit.
When this bit is a ‘1’, and MCU writes data of MAXP
length, ICIPR bit will be set automatically.
When writing a data packet smaller than MAXP length,
MCU must set ICIPR bit.
0b
6
5
R
R/W
Reserved
0b
1b
R
ICMODIN : In Control 2 Mode In bit.
Programs the endpoint direction.
1 = Direction of endpoint is set to IN.
0 = Direction of endpoint is set to OUT.
Reserved
4 : 0
R
-
Beijing Peak Microtech Co.Ltd.
CONFIDENTIAL
180
ETC [ ETC ]
