Ver 1.3
PRELIMINARY
EAGLE
3.22.2.3 USB Endpoint Interrupt Register (USBEPI)
Address : 0xFFE0_9808h
R/W
MCU USB
Default
Value
Bit
Description
31 : 5
4
R
R/
Clear
Reserved
-
0b
Set
EP4INT : EP4 Interrupt bit. (Interrupt in mode)
This bit corresponds to the endpoint 4 interrupt.
Interrupt occurs when the following conditions are satisfied.
-
-
-
When ICIPR(In Control 1 In Packet Ready) bit is cleared
When FIFO is flushed
When ICSTSTAL(In Control 1 Sent Stall) is set
3
2
R/
Clear
Set
Set
EP3INT : EP3 Interrupt bit. (Interrupt out mode)
This bit corresponds to the endpoint 3 interrupt.
Interrupt occurs when the following conditions are satisfied.
0b
0b
-
-
When OCOPR(Out Control 1 Out Packet Ready) bit is set.
When OCSTSTAL(Out Control 1 Sent Stall) bit is set.
R/
EP2INT : EP2 Interrupt bit. (Bulk in mode)
Clear
This bit corresponds to the endpoint 2 interrupt
Interrupt occurs when the following conditions are satisfied.
-
-
-
When ICIPR(In Control 1 In Packet Ready) bit is cleared
When FIFO is flushed
When ICSTSTAL(In Control 1 Sent Stall) is set
1
0
R/
Clear
Set
Set
EP1INT : EP1 Interrupt bit. (Bulk out mode)
This bit corresponds to the endpoint 1 interrupt.
Interrupt occurs when the following conditions are satisfied.
0b
0b
-
-
When OCOPR(Out Control 1 Out Packet Ready) bit is set.
When OCSTSTAL(Out Control 1 Sent Stall) bit is set.
R/
Clear
EP0INT : EP0 Interrupt bit. (Control mode)
This bit corresponds to the endpoint 0 interrupt.
Interrupt occurs when the following conditions are satisfied.
1. EP0OPR bit is set.
2. EP0IPR bit is cleared
3. EP0STSTAL bit is set
4. EP0STED bit is set
5. EP0DED bit is cleared(Indicates End of control transfer)
177
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
