ADM7008
Interface Description
Pin #
Pin Name
Type Pin Description
new 10-bit segment starting with SYNC. In 10Mb/s mode,
TXD0 must repeat each 10-bit segment 10 times.
TXD1_P2 acts as Port 2 Link/Activity LED in both SMII and
SS_SMII Mode. See LED Description for more detail.
SS_SMII Mode
LNKACT_P2,
Link and Activity LED/Port 2 SS_SMII Transmit Data. TXD0 for
port 2 inputs the data that is transmitted and is driven
SSSMII_TXD_P2
synchronously to TXCLK (pin 70). In 100Mb/s mode, TXD0
inputs a new 10-bit segment starting with SYNC. In 10Mb/s
mode, TXD0 must repeat each 10-bit segment 10 times.
Port 2 Transmit Enable. Transmit Enable for port 2 indicates
RMII Mode
TXEN_P2
94
I,
TTL that the di-bit on TXD is valid and it is driven synchronously to
REFCLK.
SMII/SS_SMII
LOW
Not Used. Tied to LOW for normal operation in SMII/SS_SMII
mode.
Power On
95, 96
I/O,
REC_10M: Value on RXD1_P1 will be latched by ADM7008
Setting
8mA, during power on reset as Port 1 10M Re-command value.
REC_10M_P1,
TESTSEL1
PD
0: Recommend Port 1 to operate in 100M Mode
1: Recommend Port 1 to operate in 10M Mode
Industrial Test Mode Select 1. Value on RXD0_P1 will be
latched by ADM7008 during power on reset as industrial test
mode select bit 1. Pull down for normal operation. For Test
Mode, See test select 0 for more detail
Port 1 RMII Receive Data. RXD[1:0] are the port 1 output di-
bits synchronously to REFCLK. Upon assertion of CRSDV_P,
RXD0 and RXD1 remain at 00 until valid data is output from the
FIFO onto RXD. The start of valid data is indicated by 01 on
RXD1 and RXD0. If a false carrier or a symbol error is
detected, RXD1 and RXD0 are set to 10 for the duration of the
activity. Note that in 100Mb/s mode RXD can change once per
REFCLK cycle, whereas in 10Mb/s mode RXD must be held
steady for 10 consecutive REFCLK cycles.
RMII Mode
RXD[1:0]_P1
Port 1 SMII Receive Data. RXD0 for the designated port
outputs data or in-band management information
synchronously to SMII REFCLK (pin 70). In 100Mb/s mode,
RXD0 outputs a new 10-bit segment starting with SYNC. In
10Mb/s mode, RXD0 must repeat each 10 bits segment 10
times. RXD1 for the designated port is acted as Speed Status
LED for port 1.
SMII Mode
SPDLED_P1,
SMII_RXD_P1
SS_SMII Mode
SPDLED_P1,
SSSMII_RXD_P
1
Port 1 SS_SMII Receive Data. RXD0 for the designated port
outputs data or in-band management information
synchronously to RXCLK (pin 75). In 100Mb/s mode, RXD0
outputs a new 10-bit segment starting with SYNC. In 10Mb/s
mode, RXD0 must repeat each 10 bits segment 10 times.
RXD1 for the designated port is acted as Speed Status LED for
port 1.
Power On
97
I/O,
Fiber/Twisted Pair Configuration bit 1. Value on RXD1 will be
ADMtek Inc.
2-13
ETC [ ETC ]
