ADM7008
Interface Description
according to rising edge of this clock.
44
PHYADDR1
I,
PHY Address Bit 1. Pure input of ADM7008. Combined with
LVTTL PHYADDR0 to form the Most Significant 2 bits of PHY address
for ADM7008. The LSB 3 bits will be assigned by ADM7008
automatically according to port number
000 Port 0
001 Port 1
010 Port 2
011 Port 3
100 Port 4
101 Port 5
110 Port 6
111 Port 7
2.2.10 LED Interface, 2 pins
Pin #
Pin Name
Type Description
50
LED_CLK
I/O,
LED Clock. Non-Continuous Clock for Serial Output LED
4mA, status. The clock high duration is 40 ns and low for 600ns.
PD
This 640 ns period forms one clock cycle and 24 clocks form
one LED burst. The first clock output is used to latch the first
bit on LED_DATA (See LED_DATA for more detail) and the
final clock is used to latch the last data on LED_DATA.
LED_CLK will be kept low for 40 ms before next LED stream
data is output.
49
LED_DATA
I/O,
LED Data. 8 port Status Output with difference sequence
4mA, according to different interface. DATA_LED is driven out by
PD
ADM7008 at the falling edge of CLK_LED. System design
should use the rising edge of LED_CLK to latch the data on
LED_DATA.
The output sequence is:
DUPCOL0 (First Bit Output) Æ DUPCOL1 Æ … Æ DUPCOL7
Æ
SPEED0 Æ SPEED1 Æ … Æ SPEED7 Æ
LNKACT0 Æ LNKACT1 Æ … Æ LNKACT7 (Last Bit Output)
2.2.11 Regulator Control, 2 pins
Pin #
Pin Name
CONTROL
Type
O,
Description
117
Regulator Control.
Analog Voltage Control to external 1.8V Regulator. See 4.2.9 for more
function description.
119
RTX
I,
Constant Voltage Reference.
Analog External 1.1kΩ1% resistor connection to ground.
2.2.12 Digital Power/Ground, 13 pins
Pin #
Pin Name
GNDO
Type
Pin Description
58, 80
Digital Ground used by 3.3V I/O.
Ground
Digital Ground used by Core.
Ground
104
46, 72,
88, 112
57, 79
GNDIK
VCC3O
Digital 3.3V Power used by I/O
ADMtek Inc.
2-17
ETC [ ETC ]
