ADM7008
Interface Description
Pin #
Pin Name
Type Pin Description
Setting
8mA latched by ADM7008 during power on reset as fiber/twisted pair
SELFX1
PD
interface configuration bit 1. Combined with SELFX0 (Power
On setting value on RXD0_P0) to program ADM7008 into 4
different modes.
00: all ports are twisted ports
01: only port 7 is fiber port, and all the other ports are twisted
ports.
10: only port 7 and port 6 are fiber ports, and all the other port
are twisted
port
11: all ports are fiber ports.
Port 1 Carrier Sense/Receive Data Valid. CRSDV_P1 asserts
when the receive medium is non-idle. The assertion of
CRSDV_P1 is asynchronous to REFCLK. At the de-assertion
of carrier, CRSDV_P1 de-asserts synchronously to REFCLK
only on the first di-bit of RXD. If there is still data in the FIFO
not yet presented onto RXD, then on the second di-bit of RXD,
CRSDV_P1 is asserted synchronously to REFCLK. The
toggling of CRSDV_P1 on the first and second di-bit continues
until all the data in the FIFO is presented onto RXD.
CRSDV_P1 is asserted for the duration of carrier activity for a
false carrier event.
RMII Mode
CRSDV_P1
SMII/SS_SMII
Mode
Not Used.
Not used in SMII and SS_SMII Mode
N/A
RMII Mode
TXD[1:0]_P1
98, 99
I,
Port 1 RMII Transmit Data. Transmit data for port 1 inputs the
TTL, di-bits that re transmitted and are driven synchronously to
PD
REFCLK. Note that in 100Mb/s mode, TXD can change once
per REFCLK cycle, whereas in 10Mb/s mode, TXD must be
held steady for 10 consecutive REFCLK cycles.
SMII Mode
Link and Activity LED/Port 1 SMII Transmit Data. TXD0 for port
1 inputs the data that is transmitted and is driven synchronously
to SMII_REFCLK (pin 70). In 100Mb/s mode, TXD0 inputs a
new 10-bit segment starting with SYNC. In 10Mb/s mode,
TXD0 must repeat each 10-bit segment 10 times.
LNKACT_P1,
SMII_TXD_P1
TXD1_P1 acts as Port 1 Link/Activity LED in both SMII and
SS_SMII Mode. See LED Description for more detail.
Link and Activity LED/Port 1 SS_SMII Transmit Data. TXD0 for
port 1 inputs the data that is transmitted and is driven
SS_SMII Mode
LNKACT_P1,
synchronously to TXCLK (pin 70). In 100Mb/s mode, TXD0
inputs a new 10-bit segment starting with SYNC. In 10Mb/s
mode, TXD0 must repeat each 10-bit segment 10 times.
Port 1 Transmit Enable. Transmit Enable for port 1 indicates
SSSMII_TXD_P1
RMII Mode
TXEN_P1
100
I,
TTL that the di-bit on TXD is valid and it is driven synchronously to
REFCLK.
SMII/SS_SMII
LOW
Not Used. Tied to LOW for normal operation in SMII/SS_SMII
mode.
ADMtek Inc.
2-14
ETC [ ETC ]
