ADM7008
Interface Description
Pin #
Pin Name
Type Pin Description
until all the data in the FIFO is presented onto RXD.
CRSDV_P3 is asserted for the duration of carrier activity for a
false carrier event.
SMII Mode
Not Used.
N/A
Not used in SMII Mode
SS_SMII Mode
RX_SYNC
SS_SMII Receive Synchronization Signal. In SS_SMII Mode,
this pin sets the bit stream alignment of SSS_SMII_RXD for all
ports.
RMII Mode
84, 85
I,
Port 3 RMII Transmit Data. Transmit data for port 3 inputs the
TXD[1:0]_P3
TTL, di-bits that re transmitted and are driven synchronously to
PD
REFCLK. Note that in 100Mb/s mode, TXD can change once
per REFCLK cycle, whereas in 10Mb/s mode, TXD must be
held steady for 10 consecutive REFCLK cycles.
SMII Mode
Link and Activity LED/Port 3 SMII Transmit Data. TXD0 for port
3 inputs the data that is transmitted and is driven synchronously
to SMII_REFCLK (pin 70). In 100Mb/s mode, TXD0 inputs a
new 10-bit segment starting with SYNC. In 10Mb/s mode,
TXD0 must repeat each 10-bit segment 10 times.
LNKACT_P3,
SMII_TXD_P3
TXD1_P3 acts as Port 3 Link/Activity LED in both SMII and
SS_SMII Mode. See LED Description for more detail.
Link and Activity LED/Port 3 SS_SMII Transmit Data. TXD0 for
port 3 inputs the data that is transmitted and is driven
SS_SMII Mode
LNKACT_P3,
synchronously to TXCLK (pin 70). In 100Mb/s mode, TXD0
inputs a new 10-bit segment starting with SYNC. In 10Mb/s
mode, TXD0 must repeat each 10-bit segment 10 times.
Port 3 Transmit Enable. Transmit Enable for port 3 indicates
SSSMII_TXD_P3
RMII Mode
TXEN_P3
86
I,
TTL that the di-bit on TXD is valid and it is driven synchronously to
REFCLK.
SMII Mode
SMII Synchronization Signal. In SMII Mode, this pin sets the bit
stream alignment of SMII_TXD and SMII_RXD for all ports.
SMII_SYNC
SS_SMII Mode
TX_SYNC
SS_SMII Transmit Synchronization Signal. In SS_SMII Mode,
this pin sets the bit stream alignment of SSS_SMII_TXD for all
ports.
REC_10M: Value on RXD1_P2 will be latched by ADM7008
during power on reset as Port 2 10M Re-command value.
0: Recommend Port 2 to operate in 100M Mode (100M)
1: Recommend Port 2 to operate in 10M Mode
Power On
89, 90
I,
Setting
PD,
PD
REC_10M_P2,
PHYADDR0
PHY Address Bit 0. Value on RXD1 will be latched by
ADM7008 during power on reset as PHY address bit 0.
Combined with PHYADDR1 (pin 44) to form PHY address for
ADM7008. See PHYADDR1 description for more detail
O,
Port 2 RMII Receive Data. RXD[1:0] are the port 2 output di-
RMII Mode
8mA bits synchronously to REFCLK. Upon assertion of CRSDV_P,
RXD0 and RXD1 remain at 00 until valid data is output from the
FIFO t
RXD Th
t t f
lid d
t i i
di t
d b
01
RXD[1:0]_P2
ADMtek Inc.
2-11
ETC [ ETC ]
