ADM7008
Interface Description
Pin #
Pin Name
Type Pin Description
FIFO onto RXD. The start of valid data is indicated by 01 on
RXD1 and RXD0. If a false carrier or a symbol error is
detected, RXD1 and RXD0 are set to 10 for the duration of the
activity. Note that in 100Mb/s mode RXD can change once per
REFCLK cycle, whereas in 10Mb/s mode RXD must be held
steady for 10 consecutive REFCLK cycles.
Port 2 SMII Receive Data. RXD0 for the designated port
outputs data or in-band management information
synchronously to SMII REFCLK (pin 70). In 100Mb/s mode,
RXD0 outputs a new 10-bit segment starting with SYNC. In
10Mb/s mode, RXD0 must repeat each 10 bits segment 10
times. RXD1 for the designated port is acted as Speed Status
LED for port 2.
SMII Mode
SPDLED_P2,
SMII_RXD_P2
Port 2 SS_SMII Receive Data. RXD0 for the designated port
outputs data or in-band management information
synchronously to RXCLK (pin 75). In 100Mb/s mode, RXD0
outputs a new 10-bit segment starting with SYNC. In 10Mb/s
mode, RXD0 must repeat each 10 bits segment 10 times.
RXD1 for the designated port is acted as Speed Status LED for
port 2.
SS_SMII Mode
SPDLED_P2,
SSSMII_RXD_P
2
Power On
Setting
91
I/O,
Duplex Recommend Value for Fiber Port. Value on this pin will
8mA be latched by ADM7008 during power on reset as duplex
FX_DUPLEX
PU
recommend value for all fiber ports.
0: Half duplex for all fiber ports.
1: Full duplex for all fiber ports.
Port 2 Carrier Sense/Receive Data Valid. CRSDV_P2 asserts
when the receive medium is non-idle. The assertion of
CRSDV_P2 is asynchronous to REFCLK. At the de-assertion
of carrier, CRSDV_P2 de-asserts synchronously to REFCLK
only on the first di-bit of RXD. If there is still data in the FIFO
not yet presented onto RXD, then on the second di-bit of RXD,
CRSDV_P2 is asserted synchronously to REFCLK. The
toggling of CRSDV_P2 on the first and second di-bit continues
until all the data in the FIFO is presented onto RXD.
CRSDV_P2 is asserted for the duration of carrier activity for a
false carrier event.
RMII Mode
CRSDV_P2
Not Used.
SMII/SS_SMII
Mode
Not used in SMII and SS_SMII Mode
N/A
RMII Mode
TXD[1:0]_P2
92, 93
I,
Port 2 RMII Transmit Data. Transmit data for port 2 inputs the
TTL, di-bits that re transmitted and are driven synchronously to
PD
REFCLK. Note that in 100Mb/s mode, TXD can change once
per REFCLK cycle, whereas in 10Mb/s mode, TXD must be
held steady for 10 consecutive REFCLK cycles.
Link and Activity LED/Port 2 SMII Transmit Data. TXD0 for port
2 inputs the data that is transmitted and is driven synchronously
to SMII_REFCLK (pin 70). In 100Mb/s mode, TXD0 inputs a
new 10 bit segment starting with SYNC
In 10Mb/s mode
SMII Mode
LNKACT_P2,
SMII_TXD_P2
ADMtek Inc.
2-12
ETC [ ETC ]
