ADM7008
Interface Description
Pin #
Pin Name
SS_SMII Mode
TXCLK
Type Pin Description
SS_SMII 125M Transmit Clock. In SS_SMII Mode, this pin acts
as 125M transmit clock for all ports. TXD and TXEN should be
synchronous to the rising edge of this clock.
Power On
Setting
81, 82
I/O,
REC_10M: Value on RXD1_P3 will be latched by ADM7008
8mA, during power on reset as Port 3 10M Re-command value.
REC_10M_P3,
ANENDIS
PD
0: Recommend Port 3 to operate in 100M Mode
1: Recommend Port 3 to operate in 10M Mode
Twisted Pair Duplex Recommend Value. Value on RXD1 will
be latched by ADM7008 during power on reset as auto
negotiation disable recommend value for twisted pair interface.
0: Auto-negotiation Enable for all twisted pair ports.
1: Auto-negotiation Disable for all twisted pair ports
Port 3 RMII Receive Data. RXD[1:0] are the port 3 output di-
bits synchronously to REFCLK. Upon assertion of CRSDV_P,
RXD0 and RXD1 remain at 00 until valid data is output from the
FIFO onto RXD. The start of valid data is indicated by 01 on
RXD1 and RXD0. If a false carrier or a symbol error is
detected, RXD1 and RXD0 are set to 10 for the duration of the
activity. Note that in 100Mb/s mode RXD can change once per
REFCLK cycle, whereas in 10Mb/s mode RXD must be held
steady for 10 consecutive REFCLK cycles.
RMII Mode
RXD[1:0]_P3
Port 3 SMII Receive Data. RXD0 for the designated port
outputs data or in-band management information
synchronously to SMII REFCLK (pin 70). In 100Mb/s mode,
RXD0 outputs a new 10-bit segment starting with SYNC. In
10Mb/s mode, RXD0 must repeat each 10 bits segment 10
times. RXD1 for the designated port is acted as Speed Status
LED for port 3.
SMII Mode
SPDLED_P3,
SMII_RXD_P3
SS_SMII Mode
SPDLED_P3,
SSSMII_RXD_P
3
Port 3 SS_SMII Receive Data. RXD0 for the designated port
outputs data or in-band management information
synchronously to RXCLK (pin 75). In 100Mb/s mode, RXD0
outputs a new 10-bit segment starting with SYNC. In 10Mb/s
mode, RXD0 must repeat each 10 bits segment 10 times.
RXD1 for the designated port is acted as Speed Status LED for
port 3.
Industrial Test Mode Select 2. Value on this pin will be latched
by ADM7008 during power on reset as industrial test mode
select bit 2. Pull down for normal operation. For Test Mode,
See test select 0 for more detail
Power On
Setting
83
I,
PD
TESTSEL2
RMII Mode
CRSDV_P3
O,
Port 3 Carrier Sense/Receive Data Valid. CRSDV_P3 asserts
8mA when the receive medium is non-idle. The assertion of
CRSDV_P3 is asynchronous to REFCLK. At the de-assertion
of carrier, CRSDV_P3 de-asserts synchronously to REFCLK
only on the first di-bit of RXD. If there is still data in the FIFO
not yet presented onto RXD, then on the second di-bit of RXD,
CRSDV_P3 is asserted synchronously to REFCLK. The
toggling of CRSDV_P3 on the first and second di-bit continues
til ll
th d
t i th FIFO
i
ADMtek Inc.
2-10
ETC [ ETC ]
