ADM7008
Interface Description
Pin #
Pin Name
Type Pin Description
I/O, REC_10M: Value on RXD1_P0 will be latched by ADM7008
Power On
105, 106
Setting
8mA, during power on reset as Port 0 10M Re-command value.
REC_10M_P0,
TESTSEL0
PD
0: Recommend Port 0 to operate in 100M Mode
1: Recommend Port 0 to operate in 10M Mode
Industrial Test Mode Select 0. Value on RXD0_P1 will be
latched by ADM7008 during power on reset as industrial test
mode select bit 0. Pull down TESTSEL[2:0] for normal
operation.
TESTSEL
Mode
000: Normal Mode
Port 0 RMII Receive Data. RXD[1:0] are the port 0 output di-
bits synchronously to REFCLK. Upon assertion of CRSDV_P,
RXD0 and RXD1 remain at 00 until valid data is output from the
FIFO onto RXD. The start of valid data is indicated by 01 on
RXD1 and RXD0. If a false carrier or a symbol error is
detected, RXD1 and RXD0 are set to 10 for the duration of the
activity. Note that in 100Mb/s mode RXD can change once per
REFCLK cycle, whereas in 10Mb/s mode RXD must be held
steady for 10 consecutive REFCLK cycles.
RMII Mode
RXD[1:0]_P0
SMII Mode
Port 0 SMII Receive Data. RXD0 for the designated port
outputs data or in-band management information
synchronously to SMII REFCLK (pin 70). In 100Mb/s mode,
RXD0 outputs a new 10-bit segment starting with SYNC. In
10Mb/s mode, RXD0 must repeat each 10 bits segment 10
times. RXD1 for the designated port is acted as Speed Status
LED for port 0.
SPDLED_P0,
SMII_RXD_P0
SS_SMII Mode
SPDLED_P0,
SSSMII_RXD_P
0
Port 0 SS_SMII Receive Data. RXD0 for the designated port
outputs data or in-band management information
synchronously to RXCLK (pin 75). In 100Mb/s mode, RXD0
outputs a new 10-bit segment starting with SYNC. In 10Mb/s
mode, RXD0 must repeat each 10 bits segment 10 times.
RXD1 for the designated port is acted as Speed Status LED for
port 0.
Power On
Setting
107
I/O,
Fiber/Twisted Pair Configuration bit 0. Value on RXD1 will be
8mA latched by ADM7008 during power on reset as fiber/twisted pair
SELFX0
PD
interface configuration bit 1. Combined with SELFX1 (Power
On setting value on RXD0_P1) to program ADM7008 into 4
different modes. See SELFX1 for more detail
RMII Mode
CRSDV_P0
Port 0 Carrier Sense/Receive Data Valid. CRSDV_P0 asserts
when the receive medium is non-idle. The assertion of
CRSDV_P0 is asynchronous to REFCLK. At the de-assertion
of carrier, CRSDV_P0 de-asserts synchronously to REFCLK
only on the first di-bit of RXD. If there is still data in the FIFO
not yet presented onto RXD, then on the second di-bit of RXD,
CRSDV_P0 is asserted synchronously to REFCLK. The
toggling of CRSDV_P0 on the first and second di-bit continues
until all the data in the FIFO is presented onto RXD.
ADMtek Inc.
2-15
ETC [ ETC ]
