ADM7008
Interface Description
Pin #
Pin Name
Type Pin Description
cycle, whereas in 10Mb/s mode RXD must be held steady for
10 consecutive REFCLK cycles.
SMII Mode
Port 5 SMII Receive Data. RXD0 for the designated port
outputs data or in-band management information
synchronously to SMII REFCLK (pin 70). In 100Mb/s mode,
RXD0 outputs a new 10-bit segment starting with SYNC. In
10Mb/s mode, RXD0 must repeat each 10 bits segment 10
times. RXD1 for the designated port is acted as Speed Status
LED for port 5.
SPDLED_P5,
SMII_RXD_P5
SS_SMII Mode
SPDLED_P5,
SSSMII_RXD_P
5
Port 5 SS_SMII Receive Data. RXD0 for the designated port
outputs data or in-band management information
synchronously to RXCLK (pin 75). In 100Mb/s mode, RXD0
outputs a new 10-bit segment starting with SYNC. In 10Mb/s
mode, RXD0 must repeat each 10 bits segment 10 times.
RXD1 for the designated port is acted as Speed Status LED for
port 5.
Power On
Setting
67
I,
Twisted Pair PAUSE Recommend Value. Value on this pin will
LVTTL, be latched by ADM7008 during power on reset as twisted pair
TP_PAUSE
PU
port (See SELFX power on setting for more detail) pause
capability control signal.
0: Pause off for all twisted pair ports
1: Pause on for all twisted pair ports
O,
Port 5 Carrier Sense/Receive Data Valid. CRSDV_P5 asserts
RMII Mode
CRSDV_P5
8mA when the receive medium is non-idle. The assertion of
CRSDV_P5 is asynchronous to REFCLK. At the de-assertion
of carrier, CRSDV_P5 de-asserts synchronously to REFCLK
only on the first di-bit of RXD. If there is still data in the FIFO
not yet presented onto RXD, then on the second di-bit of RXD,
CRSDV_P5 is asserted synchronously to REFCLK. The
toggling of CRSDV_P5 on the first and second di-bit continues
until all the data in the FIFO is presented onto RXD.
CRSDV_P5 is asserted for the duration of carrier activity for a
false carrier event.
Not Used.
SMII/SS_SMII
Mode
Not used in SMII/SS_SMII Mode
N/A
RMII Mode
TXD[1:0]_P5
68, 69
I,
Port 5 RMII Transmit Data. Transmit data for port 5 inputs the
TTL, di-bits that re transmitted and are driven synchronously to
PD
REFCLK. Note that in 100Mb/s mode, TXD can change once
per REFCLK cycle, whereas in 10Mb/s mode, TXD must be
held steady for 10 consecutive REFCLK cycles.
SMII Mode
Link and Activity LED/Port 5 SMII Transmit Data. TXD0 for port
5 inputs the data that is transmitted and is driven synchronously
to SMII_REFCLK (pin 70). In 100Mb/s mode, TXD0 inputs a
new 10-bit segment starting with SYNC. In 10Mb/s mode,
TXD0 must repeat each 10-bit segment 10 times.
LNKACT_P5,
SMII_TXD_P5
TXD1_P5 acts as Port 5 Link/Activity LED in both SMII and
SS_SMII Mode. See LED Description for more detail.
ADMtek Inc.
2-7
ETC [ ETC ]
