ADM7008
Interface Description
Pin #
Pin Name
Type Pin Description
Link and Activity LED/Port 5 SS_SMII Transmit Data. TXD0 for
SS_SMII Mode
LNKACT_P5,
port 5 inputs the data that is transmitted and is driven
synchronously to TXCLK (pin 70). In 100Mb/s mode, TXD0
inputs a new 10-bit segment starting with SYNC. In 10Mb/s
mode, TXD0 must repeat each 10-bit segment 10 times.
Port 5 Transmit Enable. Transmit Enable for port 5 indicates
SSSMII_TXD_P5
RMII Mode
TXEN_P5
70
I,
TTL that the di-bit on TXD is valid and it is driven synchronously to
REFCLK.
SMII/SS_SMII
LOW
SMII/SS_SMII Mode. Keep LOW for normal operation.
Power On
Setting
73, 74
I/O,
REC_10M: Value on RXD1_P4 will be latched by ADM7008
8mA, during power on reset as Port 4 10M Re-command value.
PD/PU 0: Recommend Port 4 to operate in 100M Mode
1: Recommend Port 4 to operate in 10M Mode
REC_10M_P4,
TP_DUPLEX
Twisted Pair Duplex Recommend Value. Value on RXD1 will
be latched by ADM7008 during power on reset as duplex
recommend value for twisted pair interface.
0: Half Duplex for all twisted pair ports
1: Full Duplex for all twisted pair ports
Port 4 RMII Receive Data. RXD[1:0] are the port 4 output di-
bits synchronously to REFCLK. Upon assertion of CRSDV_P,
RXD0 and RXD1 remain at 00 until valid data is output from the
FIFO onto RXD. 01 on RXD1 and RXD0 indicates the start of
valid data. If a false carrier or a symbol error is detected, RXD1
and RXD0 are set to 10 for the duration of the activity. Note
that in 100Mb/s mode RXD can change once per REFCLK
cycle, whereas in 10Mb/s mode RXD must be held steady for
10 consecutive REFCLK cycles.
RMII Mode
RXD[1:0]_P4
Port 4 SMII Receive Data. RXD0 for the designated port
outputs data or in-band management information
synchronously to SMII REFCLK (pin 70). In 100Mb/s mode,
RXD0 outputs a new 10-bit segment starting with SYNC. In
10Mb/s mode, RXD0 must repeat each 10 bits segment 10
times. RXD1 for the designated port is acted as Speed Status
LED for port 4.
SMII Mode
SPDLED_P4,
SMII_RXD_P4
Port 4 SS_SMII Receive Data. RXD0 for the designated port
outputs data or in-band management information
synchronously to RXCLK (pin 75). In 100Mb/s mode, RXD0
outputs a new 10-bit segment starting with SYNC. In 10Mb/s
mode, RXD0 must repeat each 10 bits segment 10 times.
RXD1 for the designated port is acted as Speed Status LED for
port 4.
SS_SMII Mode
SPDLED_P4,
SSSMII_RXD_P
4
Power On
Setting
75
I,
REFCLK Delay 2ns. Value on this pin will be latched by
LVTTL, ADM7008 during power on reset as delay select signal for
DLY2NS
PD
REFCLK input when REFCLK_SEL and RSMODE1 are both
set to 1 (RMII interface with REFCLK as clock input)
ADMtek Inc.
2-8
ETC [ ETC ]
