ADM7008
Interface Description
Pin #
Pin Name
SS_SMII Mode
SPDLED_P7,
SSS_SMII_RXD
_P7
Type Pin Description
Port 7 SS_SMII Receive Data. RXD0 for the designated port
outputs data or in-band management information
synchronously to RXCLK (pin 75). In 100Mb/s mode, RXD0
outputs a new 10-bit segment starting with SYNC. In 10Mb/s
mode, RXD0 must repeat each 10 bits segment 10 times.
RXD1 for the designated port is acted as Speed Status LED for
port 7.
53
Power On
Setting
I, LVTTL, Fiber PAUSE Recommend Value. Value on this pin will be
PD
latched by ADM7008 during power on reset as Fiber port (See
SELFX power on setting for more detail) pause capability
control signal.
FX_PAUSE
0: Pause off for all fiber ports
1: Pause on for all fiber ports
RMII Mode
CRSDV_P7
O, 8mA Port 7 Carrier Sense/Receive Data Valid. CRSDV_P7 asserts
when the receive medium is non-idle. The assertion of
CRSDV_P7 is asynchronous to REFCLK. At the de-assertion
of carrier, CRSDV_P7 de-asserts synchronously to REFCLK
only on the first di-bit of RXD. If there is still data in the FIFO
not yet presented onto RXD, then on the second di-bit of RXD,
CRSDV_P7 is asserted synchronously to REFCLK. The
toggling of CRSDV_P7 on the first and second di-bit continues
until all the data in the FIFO is presented onto RXD.
CRSDV_P7 is asserted for the duration of carrier activity for a
false carrier event.
SMII/SS_SMII
Mode N/A
Not used in SMII/SS_SMII Mode
54, 55
RMII Mode
TXD[1:0]_P7
I, TTL, Port 7 RMII Transmit Data. Transmit data for port 7 input the
PD
di-bits that re transmitted and are driven synchronously to
REFCLK.
Note: that in 100Mb/s mode, TXD can change once per
REFCLK cycle, whereas in 10Mb/s mode, TXD must be held
steady for 10 consecutive REFCLK cycles.
SMII Mode
LNKACT_P7,
SMII_TXD_P7
Link and Activity LED/Port 7 SMII Transmit Data. TXD0 for port
7 inputs the data that is transmitted and is driven synchronously
to SMII_REFCLK (pin 70). In 100Mb/s mode, TXD0 inputs a
new 10-bit segment starting with SYNC. In 10Mb/s mode,
TXD0 must repeat each 10-bit segment 10 times. TXD1_P7
acts as Port 7 Link/Activity LED in both SMII and SS_SMII
Mode. See LED Description for more detail.
SMII Mode
LNKACT_P7,
Link and Activity LED/Port 7 SS_SMII Transmit Data. TXD0 for
port 7 inputs the data that is transmitted and is driven
synchronously to TXCLK (pin 70). In 100Mb/s mode, TXD0
inputs a new 10-bit segment starting with SYNC. In 10Mb/s
mode, TXD0 must repeat each 10-bit segment 10 times.
SSSMII_TXD_P7
56
RMII Mode
TXEN_P7
I, TTL Port 7 Transmit Enable. Transmit Enable for port 7 indicates
that the di-bit on TXD is valid and it is driven synchronously to
REFCLK.
SMII/SS_SMII
LOW
TIED TO LOW. TXEN_P7 should be tied to low for normal
operation.
ADMtek Inc.
2-4
ETC [ ETC ]
