Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 390. FRM_TSLR33, Transmit Signaling Link Register 33 (COR)
Address*
Bit
Name
Function
Reset
Default
0x8LT20
15:4
3
RSVD
Reserved. Must write to 0.
0x000
0
FRM_T_TS16A Time Slot 16 Multiframe Alignment Status. A 0 indicates
that, currently, time slot 16 multiframe alignment is not estab-
lished. A 1 indicates that, currently, time slot 16 multiframe
alignment has been established.
2
FRM_T_TS16AIS Time Slot 16 AIS Detection Status. If time slot 16 multi-
frame alignment is lost, this bit will reflect the detection of AIS
in time slot 16.
0
1:0
RSVD
Reserved. Must write to 0.
00
* See Table 388 on page 275 for values of L and T.
Table 391. FRM_TSLR32, Transmit Signaling Link Register 32 (R/W)
Address* Bit
Name
Function
Reset
Default
0x8LT21
15
14
RSVD
Reserved. Must write to 0.
0
0
FRM_T_ATS16RFA Automatic TS16 Remote Frame Alarm. Enables automatic
transmission of a 1 in the Y-bit position in the transmit path
when the receive path has lost TS16 alignment.
13
12
RSVD
Reserved. Must write to 0.
0
0
FRM_T_ASPLB
Automatic Sp Loopback. When set, the Sp bit transmitted
for each individual HG will be set to 0 when the HG align-
ment is lost in the Rx path. Each Sp in the Tx path corre-
sponds to the same HG in the Rx path.
11
10
FRM_T_MSP
Manual Sp. Used to manually force the transmission of a 0
in each of the Sp bits of the HGs on each link.
0
0
FRM_T_ZCSM
Zero Code Suppression Mode. When set to 1, the signal-
ing block will give an indication to the frame formatter for
each of the data channels. This indication should disable the
zero-code suppression for the associated time slot. Signal-
ing insertion must be enabled for FRM_T_ZCSM to take
effect. FRM_T_ZCSM will not work when byte sync mapping
is enabled.
9
FRM_T_VTSIGE
VT Signaling Enable. A 1 enables the transport of signaling
to the VT mapper from the programmed signaling source in
byte sync mode. Byte sync mode cannot be enabled in con-
junction with signaling insertion (bit 8, FRM_T_SIGI). The
robbed-bit positions can be stomped while in byte sync
mode, but no signaling data can be inserted.
0
8
7
FRM_T_SIGI
RSVD
Signaling Insertion. A 1 enables the insertion of signaling
data into the Tx line. A 0 disables the insertion of signaling
data into the Tx line.
0
0
Reserved. Must write to 0.
* See Table 388 on page 275 for values of L and T.
Agere Systems Inc.
277
ETC [ ETC ]
