Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 386. FRM_RSLR33, Receive Signaling Link Register 33 (R/W) (continued)
Address* Bit
0x8LR21
Name
Function
Reset
Default
2
FRM_R_FGSRC
F and G Source. Indicates which entity will be the source for
0
the F and G values used in handling the ABCD bits.
0 = host programmed.
1 = implied by the Tx path ASM.
The Tx path option can only be selected when the Tx path is
configured with an ASM CHI or parallel system bus interface.
Also, the Tx path option can only be selected when the Rx
path is extracting data from the receive line interface vs. byte
sync VT mapped mode.
1:0 FRM_R_SIGSRC[1:0] Signaling Data Source. Indicates which of the entities will
00
be the source for the ABCD bits.
00 = signaling programmed by the host.
01 = signaling extracted from the Rx line.
10 = signaling read from VT mapper in byte sync mode (valid
only for DS1).
* See Table 383 on page 272 for values of L and R.
Table 387. Transmit Path Signaling Register Addressing Map
Address Pins (ADDR15—ADDR0)
15 14
13
LNK4 LNK3 LNK2 LNK1 LNK0 TX = 1
L* T*
12
11
10
9
8
7
0
6
5
4
3
2
1
0
0
0
SIG6 SIG5 SIG4 SIG3 SIG2 SIG1 SIG0
—
* L and T represent hexidecimal digits used for absolute addressing in Table 389, Table 390, and Table 391.
Read: for link 1 (pertaining to Table 388), the hexidecimal digit L is 0x0 and the hexidecimal digit T is 0x3.
Table 388. Transmit Path Signaling Registers Address Indexing
Link
1
L
T
Link
8
L
T
Link
16
17
18
19
20
21
22
23
L
T
Link
24
25
26
27
28
—
L
T
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
0x3
0x5
0x7
0x9
0xB
0xD
0xF
—
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x3
0x5
0x7
0x9
0xB
0xD
0xF
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x1
0x3
0x5
0x7
0x9
0xB
0xD
0xF
0x3
0x3
0x3
0x3
0x3
—
0x1
0x3
0x5
0x7
0x9
—
2
9
3
10
11
12
13
14
15
4
5
6
7
—
—
—
—
—
—
—
Agere Systems Inc.
275
ETC [ ETC ]
