Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 393. Performance Monitor Per Link Register Address Indexing
Read: for link 1 on the receive path, the hexidecimal digit L is 0x0 and the hexidecimal digit P is 0x2.
Link
L
P
Link
L
P
Link
L
P
Link
L
P
Receive Path (P is even)
1
2
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
0x2
0x4
0x6
0x8
0xA
0xC
0xE
—
8
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x0
0x2
0x4
0x6
0x8
0xA
0xC
0xE
16
17
18
19
20
21
22
23
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x0
0x2
0x4
0x6
0x8
0xA
0xC
0xE
24
25
26
27
28
—
—
—
0x3
0x3
0x3
0x3
0x3
—
0x0
0x2
0x4
0x6
0x8
—
9
3
10
11
12
13
14
15
4
5
6
7
—
—
—
—
—
Transmit Path (P is odd)
1
2
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
0x3
0x5
0x7
0x9
0xB
0xD
0xF
—
8
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x3
0x5
0x7
0x9
0xB
0xD
0xF
16
17
18
19
20
21
22
23
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x1
0x3
0x5
0x7
0x9
0xB
0xD
0xF
24
25
26
27
28
—
—
—
0x3
0x3
0x3
0x3
0x3
—
0x1
0x3
0x5
0x7
0x9
—
9
3
10
11
12
13
14
15
4
5
6
7
—
—
—
—
—
Table 394. FRM_PMLR1, Performance Monitor Link Register 1 (R/W)
Address* Bit Name Function
Reset
Default
0x8LP80 15:0 FRM_PM_IM4[15:0] Performance Monitoring Register FRM_PMLR4 Inter-
rupt Mask. A 1 masks the corresponding status bit in the
interrupt status registers (Table 398 on page 287) from
generating an interrupt. A 0 allows an interrupt to be gener-
ated.
0xFFFF
* See Table 393 for values of L and P.
Table 395. FRM_PMLR2, Performance Monitor Link Register 2 (R/W)
Address* Bit
Name
Function
Reset
Default
0x8LP81 15:0 FRM_PM_IM5[15:0] Performance Monitor Register FRM_PMLR5 Interrupt
Mask. A 1 masks the corresponding status bit in interrupt
0xFFFF
status registers (Table 398 on page 287) from generating
an interrupt. A 0 allows an interrupt to be generated.
* See Table 393 for values of L and P.
Agere Systems Inc.
279
ETC [ ETC ]
