Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 384. FRM_RSLR0—FRM_RSLR31, Receive Signaling Link Registers 0—31 (R/W)
Address*
Bit
Name
Function
Reset
Default
Time Slot 0 Receive Signaling Data.
Time Slot 1 Receive Signaling Data.
Time Slot 2 Receive Signaling Data.
Time Slot 3 Receive Signaling Data.
Time Slot 4 Receive Signaling Data.
Time Slot 5 Receive Signaling Data.
Time Slot 6 Receive Signaling Data.
Time Slot 7 Receive Signaling Data.
Time Slot 8 Receive Signaling Data.
Time Slot 9 Receive Signaling Data.
Time Slot 10 Receive Signaling Data.
Time Slot 11 Receive Signaling Data.
Time Slot 12 Receive Signaling Data.
Time Slot 13 Receive Signaling Data.
Time Slot 14 Receive Signaling Data.
Time Slot 15 Receive Signaling Data.
Time Slot 16 Receive Signaling Data.
Time Slot 17 Receive Signaling Data.
Time Slot 18 Receive Signaling Data.
Time Slot 19 Receive Signaling Data.
Time Slot 20 Receive Signaling Data.
Time Slot 21 Receive Signaling Data.
Time Slot 22 Receive Signaling Data.
Time Slot 23 Receive Signaling Data.
Time Slot 24 Receive Signaling Data.
Time Slot 25 Receive Signaling Data.
Time Slot 26 Receive Signaling Data.
Time Slot 27 Receive Signaling Data.
Time Slot 28 Receive Signaling Data.
Time Slot 29 Receive Signaling Data.
Time Slot 30 Receive Signaling Data.
Time Slot 31 Receive Signaling Data.
0x8LR00
0x8LR01
0x8LR02
0x8LR03
0x8LR04
0x8LR05
0x8LR06
0x8LR07
0x8LR08
0x8LR09
0x8LR0A
0x8LR0B
0x8LR0C
0x8LR0D
0x8LR0E
0x8LR0F
0x8LR10
0x8LR11
0x8LR12
0x8LR13
0x8LR14
0x8LR15
0x8LR16
0x8LR17
0x8LR18
0x8LR19
0x8LR1A
0x8LR1B
0x8LR1C
0x8LR1D
0x8LR1E
0x8LR1F
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
FRM_RPSR0[6:0]
FRM_RPSR1[6:0]
FRM_RPSR2[6:0]
FRM_RPSR3[6:0]
FRM_RPSR4[6:0]
FRM_RPSR5[6:0]
FRM_RPSR6[6:0]
FRM_RPSR7[6:0]
FRM_RPSR8[6:0]
FRM_RPSR9[6:0]
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
6:0 FRM_RPSR10[6:0]
6:0 FRM_RPSR11[6:0]
6:0 FRM_RPSR12[6:0]
6:0 FRM_RPSR13[6:0]
6:0 FRM_RPSR14[6:0]
6:0 FRM_RPSR15[6:0]
6:0 FRM_RPSR16[6:0]
6:0 FRM_RPSR17[6:0]
6:0 FRM_RPSR18[6:0]
6:0 FRM_RPSR19[6:0]
6:0 FRM_RPSR20[6:0]
6:0 FRM_RPSR21[6:0]
6:0 FRM_RPSR22[6:0]
6:0 FRM_RPSR23[6:0]
6:0 FRM_RPSR24[6:0]
6:0 FRM_RPSR25[6:0]
6:0 FRM_RPSR26[6:0]
6:0 FRM_RPSR27[6:0]
6:0 FRM_RPSR28[6:0]
6:0 FRM_RPSR29[6:0]
6:0 FRM_RPSR30[6:0]
6:0 FRM_RPSR31[6:0]
* See Table 383 on page 272 for values of L and R.
Notes:
Bit 0 = A, bit 1 = B, bit 2 = C, bit 3 = D, bit 5 = F, and bit 6 = G.
Register includes the following bits: F, G—selects 2, 4, 16, or no state signaling mode; A, B, C, D—signaling data.
For DS1 links, address locations 1 through 24 will contain valid data.
For CEPT links, locations 1 through 15 and 17 through 31 will contain valid data. Writes from the system interface to address 0 and 16 will be
accepted and stored in signaling registers.
Agere Systems Inc.
273
ETC [ ETC ]
