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TMXF281553BAL-3C-DB 参数 Datasheet PDF下载

TMXF281553BAL-3C-DB图片预览
型号: TMXF281553BAL-3C-DB
PDF下载: 下载PDF文件 查看货源
内容描述: 电信/数据通信\n [Telecomm/Datacomm ]
分类和应用: 电信数据通信
文件页数/大小: 784 页 / 10078 K
品牌: ETC [ ETC ]
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TMXF28155 Supermapper  
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1  
Data Sheet  
June 2002  
12 28-Channel Framer Registers (continued)  
Table 385. FRM_RSLR32, Receive Signaling Link Register 32 (COR)  
Address* Bit  
Name  
Function  
Reset  
Default  
0x8LR20 15:1 FRM_R_HGAIS[3:0] HG AIS Detection. Indicates the detection of AIS in the cor-  
0000  
0000  
2
responding HG.  
11:8  
FRM_R_HGA[3:0]  
HG Alignment. Indicates the alignment status for the corre-  
sponding HG. A 0 indicates no alignment. A 1 indicates align-  
ment for the corresponding group.  
7:4 FRM_R_HGRDI[3:0] HG RDI. Indicates the detection of three consecutive zeros in 0000  
the Sp bit position of the corresponding HG.  
3
FRM_R_TS16A  
Time Slot 16 Multiframe Alignment Status. A 0 indicates  
that, currently, time slot 16 multiframe alignment is not estab-  
lished. A 1 indicates that, currently, time slot 16 multiframe  
alignment has been established.  
0
2
FRM_R_TS16AIS  
RSVD  
Time Slot 16 AIS Detection Status. If time slot 16 multi-  
frame alignment is lost, this bit will reflect the detection of AIS  
in time slot 16.  
0
0
1:0  
Reserved. Must write to 0.  
* See Table 383 on page 272 for values of L and R.  
Table 386. FRM_RSLR33, Receive Signaling Link Register 33 (R/W)  
Address* Bit  
Name  
Function  
Reset  
Default  
0x8LR21 15  
FRM_R_FZCON  
Freeze Conversion. When set to 1, this enables the conver-  
sion of certain signaling codes when the signaling buffers  
have been frozen. The code translation is 00 to 01 and 0000  
to 0101 for 4-state and 16-state signaling, respectively.  
0
14:9  
8
RSVD  
Reserved. Must write to 0.  
0
0
FRM_R_SIGI  
Signaling Insertion. A 1 enables the insertion of signaling  
data into the Tx line. A 0 disables the insertion of signaling  
data into the Tx line. This bit is valid in the Rx path only when  
in transport mode; otherwise, it should be set to 0.  
7
FRM_R_RXSTOMP Rx Path Stomping. For DS1 links, this bit indicates to stomp  
all robbed bit signaling on voice time slots on the correspond-  
ing link. Stomping of time slot 16 for CEPT links is performed  
in the system interface block.  
1 = will enable stomping.  
0 = will disable stomping for the corresponding link.  
6
5
RSVD  
Reserved. Must write to 0.  
FRM_R_SIGDEB  
Signaling Debounce.This bit enables signal debounce on  
signaling when extracted from the Rx line.  
0
0
4
FRM_R_HGEN  
Handling Group Enable. When set to 1 in combination with  
selecting the source of signaling data to be the VT mapper,  
this indicates to the signaling block that the signaling for this  
link is byte sync mapped and uses the handling group format.  
3
FRM_R_MSIGFZ  
Manual Signaling Freeze. Used to manually halt the signal-  
ing register updates when the source of signaling data is  
either the VT mapper or when the signaling is extracted from  
the Rx line. A 1 halts the updates.  
0
* See Table 383 on page 272 for values of L and R.  
274  
Agere Systems Inc.  
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