TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
Data Sheet
June 2002
June 2002
TMXF28155/51 Supermapper
12 28-Channel Framer Registers (continued)
Table 391. FRM_TSLR32, Transmit Signaling Link Register 32 (R/W) (continued)
Address* Bit
Name
Function
Reset
Default
0x8LT21
6
FRM_T_TXSTOMP Tx Path Stomping. For DS1 links, this bit indicates to stomp
all robbed-bit signaling on voice time slots on the corre-
sponding link to 0. Stomping time slot 16 for CEPT links is
done by inserting all ones using the signaling registers. A 1
will enable stomping. A 0 will disable stomping for the corre-
sponding link.
0
5
4
RSVD
Reserved. Must write to 0.
0
0
FRM_T_HGEN
Handling Group Enable. When set to 1 in combination with
(bit 9, FRM_T_VTSIGE), this bit indicates to the signaling
block that the signaling for this link is byte sync mapped and
uses the handling group format.
3
2
FRM_T_MSIGFZ
FRM_T_FGSRC
Manual Signaling Freeze. Used to manually halt the signal-
ing register updates when the source of signaling data is
either the Rx system or the Rx line. A 1 halts the updates.
0
0
F and G Source. Indicates which entity will be the source
for the F and G values used in handling the ABCD bits.
0 = host programmed.
1 = sourced from the Rx system interface.
The F and G programming can be implied by the system
interface only when using the ASM CHI or the parallel sys-
tem interface.
1:0 FRM_T_SIGSRC[1:0] Signaling Data Source. Indicates which of the entities will
00
be the source for the ABCD bits.
00 = signaling programmed by the host.
01 = signaling extracted from the Rx line.
10 = signaling received from the system interface.
* See Table 388 on page 275 for values of L and T.
12.10 Performance Monitor Per Link Registers
The following tables describe the functions of all bits in the register map. Counters are programmable to either
roll over or saturate, and may be programmed to clear on read.
Registers are only provisionable to clear-on-read (COR).
For each address, the register bits are identified as either read/write (R/W) or read only (RO), and the value of the
bits on reset are given.
Table 392. Performance Monitor Per Link Register Addressing Map
Address Pins (ADDR15—ADDR0)
15 14
13
12
11
10
9
8
7
1
6
0
5
4
3
2
1
0
0
0
LNK4 LNK3 LNK2 LNK1 LNK0
RXP = 0
TXP = 1
PM5 PM4 PM3 PM2 PM1 PM0
L*
P*
—
* L and P represent hexidecimal digits used for absolute addressing in Table 394 through Table 413.
278
Agere Systems Inc.
ETC [ ETC ]
