TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
12 28-Channel Framer Registers (continued)
Table 389. FRM_TSLR0—FRM_TSLR31, Transmit Signaling Link Registers 0—31 (R/W)
Address*
Bit
Name
Function
Reset
Default
Time Slot 0 Transmit Signaling Data.
Time Slot 1 Transmit Signaling Data.
Time Slot 2 Transmit Signaling Data.
Time Slot 3 Transmit Signaling Data.
Time Slot 4 Transmit Signaling Data.
Time Slot 5 Transmit Signaling Data.
Time Slot 6 Transmit Signaling Data.
Time Slot 7 Transmit Signaling Data.
Time Slot 8 Transmit Signaling Data.
Time Slot 9 Transmit Signaling Data.
Time Slot 10 Transmit Signaling Data.
Time Slot 11 Transmit Signaling Data.
Time Slot 12 Transmit Signaling Data.
Time Slot 13 Transmit Signaling Data.
Time Slot 14 Transmit Signaling Data.
Time Slot 15 Transmit Signaling Data.
Time Slot 16 Transmit Signaling Data.
Time Slot 17 Transmit Signaling Data.
Time Slot 18 Transmit Signaling Data.
Time Slot 19 Transmit Signaling Data.
Time Slot 20 Transmit Signaling Data.
Time Slot 21 Transmit Signaling Data.
Time Slot 22 Transmit Signaling Data.
Time Slot 23 Transmit Signaling Data.
Time Slot 24 Transmit Signaling Data.
Time Slot 25 Transmit Signaling Data.
Time Slot 26 Transmit Signaling Data.
Time Slot 27 Transmit Signaling Data.
Time Slot 28 Transmit Signaling Data.
Time Slot 29 Transmit Signaling Data.
Time Slot 30 Transmit Signaling Data.
Time Slot 31 Transmit Signaling Data.
0x8LT00
0x8LT01
0x8LT02
0x8LT03
0x8LT04
0x8LT05
0x8LT06
0x8LT07
0x8LT08
0x8LT09
0x8LT0A
0x8LT0B
0x8LT0C
0x8LT0D
0x8LT0E
0x8LT0F
0x8LT10
0x8LT11
0x8LT12
0x8LT13
0x8LT14
0x8LT15
0x8LT16
0x8LT17
0x8LT18
0x8LT19
0x8LT1A
0x8LT1B
0x8LT1C
0x8LT1D
0x8LT1E
0x8LT1F
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
6:0
FRM_TPSR0[6:0]
FRM_TPSR1[6:0]
FRM_TPSR2[6:0]
FRM_TPSR3[6:0]
FRM_TPSR4[6:0]
FRM_TPSR5[6:0]
FRM_TPSR6[6:0]
FRM_TPSR7[6:0]
FRM_TPSR8[6:0]
FRM_TPSR9[6:0]
FRM_TPSR10[6:0]
FRM_TPSR11[6:0]
FRM_TPSR12[6:0]
FRM_TPSR13[6:0]
FRM_TPSR14[6:0]
FRM_TPSR15[6:0]
FRM_TPSR16[6:0]
FRM_TPSR17[6:0]
FRM_TPSR18[6:0]
FRM_TPSR19[6:0]
FRM_TPSR20[6:0]
FRM_TPSR21[6:0]
FRM_TPSR22[6:0]
FRM_TPSR23[6:0]
FRM_TPSR24[6:0]
FRM_TPSR25[6:0]
FRM_TPSR26[6:0]
FRM_TPSR27[6:0]
FRM_TPSR28[6:0]
FRM_TPSR29[6:0]
FRM_TPSR30[6:0]
FRM_TPSR31[6:0]
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
* See Table 388 on page 275 for values of L and T.
Notes:
Bit 0 = A, bit 1 = B, bit 2 = C, bit 3 = D, bit 5 = F, and bit 6 = G.
Register includes the following bits: F, G—selects 2, 4, 16, or no state signaling mode; A, B, C, D—signaling data.
For DS1 links, address locations 1 through 24 will contain valid data.
For CEPT links, locations 1 through 15 and 17 through 31 will contain valid data. Writes from the system interface to address 0 and 16 will be
accepted and stored in signaling registers. For CEPT links, inserted time slot 16 X bits are written to locates 0.
276
Agere Systems Inc.
ETC [ ETC ]
