Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 323. FRM_PMGR1, Performance Monitor Global Register 1 (COR)
Address* Bit
Name
Function
Reset
Default
0x80P30 15:2
1
RSVD
Reserved. Must write to 0.
0x0000
0
FRM_DETECT Test-Pattern Detect. A 1 indicates the pattern detector has
locked onto the pattern specified by the FRM_PTRN_SEL[3:0]
(Table 336 on page 256) configuration bits. There is only one
test-pattern detector. See O.151, Section 2. Both framed and
unframed test-pattern generation/detection are supported.
0
FRM_PTRNBER Test-Pattern Bit Error. A 1 indicates the receive framer pattern
detector has found one or more single-bit errors in the pattern on
to which it is currently locked. There is only one test-pattern BER
counter for all links.
0
*
P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Table 324. FRM_PMGR2, Performance Monitor Global Register 2 (COR)
Address*
Bit
Name
Function
Reset
Default
0x80P31
15:0 FRM_TPERR_CT[15:0] Test Pattern Error Count Register. This register con-
0
tains the 16-bit count of test-pattern errors.
*
P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Table 325. FRM_PMGR3, Performance Monitor Global Register 3 (R/W)
Address*
Bit
Name
Function
Reset
Default
0x80P32 15:14
13:11
RSVD
Reserved. Must write to 0.
CEPT Mode RAI Activation Count†.
CEPT Mode RAI Deactivation Count†. RAC and RDC
00
FRM_RAC[2:0]
FRM_RDC[2:0]
001
001
10:8
can be set to meet various standards.
7
FRM_FSFBEEN
FS Frame Bit Error Enable. Allows a signaling frame (FS)
bit error to set the FBE status bit, FRM_FBE (Table 398 on
page 287).
0
In DDS, a 0 means do not count TS24 framing and FS as
FBEs; a 1 means count TS24 framing and Fs as FBEs.
0 = FS bit errors disabled.
1 = FS bit errors enabled.
6
5
FRM_CMFRFEN
FRM_CRCRFEN
CEPT Multiframe Reframe Enable.
0 = CEPT CRC-4 multiframe reframe disabled.
0
1
1 = CEPT CRC-4 multiframe reframe enabled. A research
for multiframe alignment is initiated upon a loss of
CEPT CRC-4 multiframe alignment.
CRC Reframe Enable.
0 = CRC errors do not cause a reframe or LOF condition.
1 = the receive performance monitor will force a reframe
and LOF condition on excessive CRC errors.
* P = 0x0 for the receive path, and P = 0x1 for the transmit path.
† FRM_RACFRM_RDC Standard.
Agere Systems Inc.
251
ETC [ ETC ]
