TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
12 28-Channel Framer Registers (continued)
Table 321. FRM_FGR5, Framer Global Register 5 (COR)
Address
Bit
Name
Function
Reset
Default
Reserved. Must write to 0.
0x80015
15:12
RSVD
000
11:0 FRM_TPSSEI[28:17] Transmit Path System Synchronization Error Inter- 000000000
rupt.
000
1 = indicates a transmit path system synchronization
error on links 28 to 17.
12.3 Performance Monitor Global Registers
Table 322. FRM_PMGR1_B, Performance Monitor Global Register 1_B (R/W)
Address* Bit
Name
Function
Reset
Default
0x80P20 15
FRM_SEC_SEL
Framer PMRESET Source. The source of the performance
monitoring interval (generally one second) may be selected to
be internal to the framer block or external to the framer block.
0
0 = external.
1 = internal.
14 FRM_GLB_PL_CFG Global/Per-Link Configuration. This bit is used to select glo-
bal RAC/RDC or per-link RAC/RDC. This bit selects global
reframe upon excessive CRC errors or per-link reframe upon
excessive CRC errors. When FRM_GLB_PL_CFG = 0, global
RAC/RDC is selected. The configurations in FRM_RAC
0
(0x80P32 bits [13:11]) and FRM_RDC (0x80P32 bits [10:8])
are used for all the applicable links. Reframe upon excessive
CRC errors is determined by FRM_CRCRFEN (0x80P32,
bit 5), which affects all the applicable links. When
FRM_GLB_PL_CFG = 1, per-link RAC/RDC is selected. The
configurations in FRM_PL_RAC (0x8LP94 bits [5:3]) and
FRM_PL_RDC (0x8LP94 bits [2:0]) are used for each individ-
ual link. Reframe upon excessive CRC errors is determined by
FRM_PL_CRCRFEN (0x8LP94, bit 8) for each individual link.
13
RSVD
Reserved. Must write to 0.
000
12:0 FRM_CT125[12:0] Framer Terminal Count. This is the terminal count for an
internal 125 µs timer that is multiplied by 8000 to determine
the internal performance monitoring interval. This count is
based on the TDM clock speed. The default count is based on
a 51.84 MHz clock. This terminal count is calculated by the fol-
lowing equation:
0x1950
Timer terminal count = (125 µs)(fTDM clock).
*
P = 0x0 for the receive path, and P = 0x1 for the transmit path.
250
Agere Systems Inc.
ETC [ ETC ]
