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TMXF281553BAL-3C-DB 参数 Datasheet PDF下载

TMXF281553BAL-3C-DB图片预览
型号: TMXF281553BAL-3C-DB
PDF下载: 下载PDF文件 查看货源
内容描述: 电信/数据通信\n [Telecomm/Datacomm ]
分类和应用: 电信数据通信
文件页数/大小: 784 页 / 10078 K
品牌: ETC [ ETC ]
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Data Sheet  
June 2002  
TMXF28155 Supermapper  
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1  
12 28-Channel Framer Registers (continued)  
Table 318. FRM_FGR2, Framer Global Register 2 (R/W)  
Address  
Bit  
Name  
Function  
Reset  
Default  
Terminal Count Enable.  
0x80011  
15  
FRM_TC_EN  
0
0 = terminal count disabled use defaults.  
1 = terminal count enabled.  
Reserved. Must write to 0.  
14:8  
7:0  
RSVD  
0000000  
FRM_TC[7:0] Terminal Count. When enabled, the link counter will count  
from 1 to the terminal count. The terminal count determines  
the number of links available for use. The operational links are  
link 1 to the link determined by the terminal count. By default,  
the count is determined by the option bit, FRM_DS1_CEPTN  
(Table 313 on page 246). In an application, where there is a  
mix of DS1 and CEPT links or a small number of links, the ter-  
minal count may be set by enabling FRM_TC_EN and setting  
the terminal count, FRM_TC[7:0].  
00011100  
Note: Minimum terminal count value is 4.  
Table 319. FRM_FGR3, Framer Global Register 3 (R/W)  
Address  
Bit  
Name  
Function  
Reset  
Default  
0x80012  
15  
FRM_TPSSE_IM Transmit Path System Synchronization Error Inter-  
rupt Mask. A transmit path system synchronization error  
interrupt is generated when synchronization is lost  
between the receive system interface and the transmit  
path line clock. FRM_TPSSE_IM is a global mask for the  
interrupt status from each link. The individual link transmit  
path system error interrupt status bits,  
1
FRM_TPSSEI[28:1] are summarized in FRM_AR_IS bit  
14 of FRM_SFGR3 (Table 315 on page 248).  
0 = allows any synchronization error, as reported in the  
synchronization status registers, to generate an inter-  
rupt.  
1 = masks any synchronization error, as reported in the  
synchronization status registers, from generating an  
interrupt.  
14:0  
RSVD  
Reserved. Must write to 0.  
000000000  
000000  
Table 320. FRM_FGR4, Framer Global Register 4 (COR)  
Address  
Bit  
Name  
Function  
Reset  
Default  
0x80014  
15:0 FRM_TPSSEI[16:1] Transmit Path System Synchronization Error Inter-  
00X0000  
rupt.  
1 = indicates a transmit path system synchronization  
error on links 16 to 1.  
Agere Systems Inc.  
249  
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