TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
12 28-Channel Framer Registers (continued)
Table 315. FRM_SFGR3, Superframer Global Register 3 (RO)
Address
Bit
15
14
13
12
11
10
9
Name
Function
Reset
Default
0x80002
FRM_RP_SIG
FRM_AR_IS
A 1 indicates the change of signaling state; FIFO con-
tains state change information.
0
A 1 indicates the FRM_AR_IS block has generated an
interrupt.
0
0
0
0
0
0
0
0
0
0
0
0
FRM_TP_RDL_IS A 1 indicates the FRM_TP_RDL_IS block has generated
an interrupt.
FRM_TP_TDL_IS A 1 indicates the FRM_TP_TDL_IS block has generated
an interrupt.
FRM_RH_IS
A 1 indicates the FRM_RH_IS block has generated an
interrupt.
FRM_TH_IS
A 1 indicates the FRM_TH_IS block has generated an
interrupt.
FRM_TS_IS
A 1 indicates the FRM_TS_IS block has generated an
interrupt.
8
FRM_RS_IS
A 1 indicates the FRM_RS_IS block has generated an
interrupt.
7
FRM_TP_PM_IS
FRM_RP_PM_IS
A 1 indicates the FRM_TP_PM_IS block has generated
an interrupt.
6
A 1 indicates the FRM_RP_PM_IS block has generated
an interrupt.
5
FRM_RP_RDL_IS A 1 indicates the FRM_RP_RDL_IS block has generated
an interrupt.
4
FRM_RP_TDL_IS A 1 indicates the FRM_RP_TDL_IS block has generated
an interrupt.
3:0
RSVD
Reserved. Reads 0.
Table 316. FRM_SFGSR4, Superframer Global Register 4 (R/W)
Address
Bit
Name
Function
Reset
Default
Reserved. Must write to 0.
0x80003
15
RSVD
0
Superframer Version Number.
14:12 FRM_VERSION[2:0]
000
Reserved. Must write to 0.
11:0
RSVD
0x000
12.2 Arbiter (Framer) Global Registers
Table 317. FRM_FGR1, Framer Global Register 1 (R/W)
Address
Bit
Name
Function
Reset
Default
Disable Loss of High-Speed Clock Detection.
0x80010
15
FRM_DIS_LHSCD
0
1 = disable the loss of high-speed clock detection within
the framer.
Reserved. Must write to 0.
14:0
RSVD
—
248
Agere Systems Inc.
ETC [ ETC ]
