TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
Data Sheet
June 2002
June 2002
TMXF28155/51 Supermapper
12 28-Channel Framer Registers (continued)
Table 325. FRM_PMGR3, Performance Monitor Global Register 3 (R/W) (continued)
Address*
Bit
Name
Function
Reset
Default
0x80P32
4:3 FRM_CEPTAISM[1:0] CEPT AIS Mode.
01
00 = option 0: G.775, Section I.2; G.965, Section 16.1.2.
01 = option 1: G.775, Section 5.2.
10 = option 2: G.775, Section I.2.
11 = option 3: G.775, Section I.2.
DS1 AIS Mode.
2
FRM_DS1AISM
1
0 = option 0: T1.231, Section 6.1.2.2.3, T1.403, Section H,
G.775, Section 5.4.
1 = option 1: G.775, Section I.2.
1
0
FRM_ESFRAIM
FRM_RAICLR
ESF RAI Mode.
0
0
0 = alternating eight ones followed by eight zeros.
1 = all ones.
Clear RAI on Reception of DS1 Idle Signal.
0 = ignore DS1 idle signal for RAI clearing.
1 = clear failure on reception of DS1 idle signal: ANSI
T1.231, Section 6.2.2.2.1.
Table 326. FRM_PMGR4, Performance Monitor Global Register 4 (R/W)
Address* Bit Name Function
Reset
Default
0x80P33 15:0 FRM_SFSEST[15:0] SF Severely Errored Second Threshold for All SF For-
0x0140
matted Channels.
Note: A bursty errored second will be recorded if the number
of events is greater than the errored second threshold
but less than the severely errored second threshold.
There is a separate threshold for ESF and SF because
of the bit error provisioning in ESF (Ft or Fs).
*
P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Table 327. FRM_PMGR5, Performance Monitor Global Register 5—PMGR5 (R/W)
Address* Bit Name Function
Reset
Default
0x80P34 15:0 FRM_DCT[15:0] DS1 Excessive CRC Threshold—Default 320. This register
sets the 1 s CRC threshold at which an excessive CRC error con-
dition is reported, and the 1 s CRC threshold at which a reframe
may be forced.
0x0140
*
P = 0x0 for the receive path, and P = 0x1 for the transmit path.
252
Agere Systems Inc.
ETC [ ETC ]
