Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 314. FRM_SFGR2, Superframer Global Register 2 (R/W)
Address Bit
Name
Function
Reset
Default
0x80001 15:14
13
RSVD
Reserved. Must write to 0.
0
0
FRM_TP_SIG_PWDN Transmit Path Receive Signaling Powerdown. When set
to 0, the transmit path receive signaling block for the trans-
port mode is powered down.
12
11
FRM_RP_SIG_PWDN Receive Path Transmit Signaling Powerdown. When set
to 0, the receive path transmit signaling block for the trans-
port mode is powered down.
0
0
0
0
0
FRM_TP_RDL_PWDN Transmit Path Receive Datalink Powerdown. When set to
0, the transmit path receive data link block for the transport
mode is powered down.
10 FRM_RP_TDL_PWDN Receive Path Transmit Datalink Powerdown. When set to
0, the receive path transmit data link block for the transport
mode is powered down.
9
FRM_TP_RH_PWDN Transmit Path Receive HDLC Powerdown. When set to 0,
the transmit path receive HDLC block for the transport mode
is powered down.
8
FRM_RP_TH_PWDN Receive Path Transmit HDLC Powerdown. When set to 0,
the receive path transmit HDLC block for the transport mode
is powered down.
7
6
5
FRM_TS_PWDN
Transmit Path System Block Powerdown. When set to 0,
the transmit path system block is powered down.
0
0
0
FRM_RS_PWDN
Receive Path System Block Powerdown. When set to 0,
the receive path system block is powered down.
FRM_TP_PM_PWDN Transmit Path Performance Monitor Powerdown. When
set to 0, the transmit path performance monitor block is pow-
ered down.
4
3
FRM_RP_FF_PWDN Receive Path Frame Formatter Powerdown. When set to
0
0
0
0, the receive path frame formatter block is powered down.
FRM_TP_RA_PWDN Transmit Path Receive Aligner Powerdown. When set to
0, the transmit path receive aligner block is powered down.
2:0
RSVD
Reserved. Must write to 0.
Agere Systems Inc.
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