TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
12 28-Channel Framer Registers (continued)
Table 332. FRM_PMGR10, Performance Monitor Global Register 10 (R/W)
These bits enable the errored events used to determine errored and severely errored seconds in the CEPT modes.
Address* Bit
Name
Function
Reset
Default
0x80P39
15
14
13
12
11
10
9
FRM_CSA6_F CEPT Sa6 = F Enable and Sa5 = 1. (Reception of AIS.)
FRM_CSA6_E CEPT Sa6 = E Enable and Sa5 = 1. (FC3 and FC4.)
FRM_CSA6_C CEPT Sa6 = C Enable and Sa5 = 1. (LOS/LFA.)
FRM_CSA6_8 CEPT Sa6 = 8 Enable and Sa5 = 1. (Loss of power.)
FRM_CSA6_1X CEPT Sa6 = 001x Event Enable.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FRM_CSA6_X1 CEPT Sa6 = 00x1 Event Enable.
FRM_CEBIT
FRM_CLMFA
FRM_CLFA
FRM_CRFA
FRM_CSLIP
FRM_CLOS
FRM_CAIS
FRM_CCRC
CEPT E bit = 0 Event Enable.
8
CEPT Loss of Multiframe Alignment Enable.
CEPT Loss of Frame Alignment Enable.
CEPT Remote Frame Alarm Enable.
CEPT Slip Enable.
7
6
5
4
CEPT Loss of Signal Enable.
3
CEPT Alarm Indication Signal Enable.
CEPT CRC-4 Error Enable.
2
1
FRM_CNOTFAS CEPT Non-FAS Bit Error Enable.
FRM_CFAS CEPT FAS Bit Error Enable.
0
*
P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Table 333. FRM_PMGR11, Performance Monitor Global Register 11 (R/W)
Address* Bit Name Function
Reset
Default
0x80P3A 15:0 FRM_CRET[15:0] Continuous Received E-Bit Threshold—Default 991. This
register sets the 5 s continuous E-bit threshold for setting the
CRE bit status indication.
0x03DF
*
P = 0x0 for the receive path, and P = 0x1 for the transmit path.
254
Agere Systems Inc.
ETC [ ETC ]
